Test cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.

Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing the test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this article, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.

As the complexity of industrial integrated circuits continue to increase rapidly, test data compression has now become a de facto technology for large designs to reduce the overall test cost. During the design for test (DFT) planning, it is critical to understand the impact of using different numbers of input/output test channels on test coverage, test cycles, and test data volume. In this paper, two approaches to predict the test pattern counts and test data volumes with different input channel counts are presented, one with the compression tool able to generate channel-scaling patterns and the other without this capability. The results can be used to determine the scan test configuration that results in the smallest or near smallest test data volume. Experiments on industrial circuits show that the average error rates of pattern count prediction for most circuits are less than 10% for both approaches. The error rates of the predicted smallest data volumes are all less than 3.5%. The total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error approach.

This article presents a next-generation test data compression scheme. It builds on the isometric compression paradigm, but makes it more flexible and elevates encoding efficiency to values unachievable through state-of-the-art sequential compression schemes. Furthermore, its programmable selection of full-toggle scan chains ensures high test coverage and virtually eliminates compression aborts. The presented approach follows from a fundamental observation that among test cube care bits, only a very few have a status of necessary assignments (their locations cannot be changed), whereas the remaining ones have alternative sites. These test cubes are used to form circular test templates which synergistically control a decompressor and guide back ATPG to find assignments yielding highly compressible test patterns. A redesigned low-silicon-area decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. The experimental results obtained for large industrial designs and other benchmark circuits confirm the superiority of the proposed scheme over existing techniques and are reported herein.

Timing exceptions are commonly used to indicate that the timing of certain paths have been relaxed so as to enable the design to meet timing closure. Generating scan-based test patterns without considering timing exceptions can lead to invalid test responses, resulting in unpredictable test quality impact. The existing simulation-based solution masks out unreliable signals after a test pattern is generated. If the signals required for detecting the target fault are unreliable and masked out, the generated test pattern fails to detect the target fault, and it is discarded. To achieve an acceptable test coverage, several iterations of test generation with a randomized decision-making process are typically required where different tests are generated for target faults. In this paper, an innovative deterministic ATPG algorithm called TEA (Timing Exception ATPG) is proposed to prevent the generated test patterns from being impacted by timing exceptions. The deterministic algorithm is compatible with the existing simulation-based approach. In this simulation environment, TEA is complete such that for a target fault, the test pattern generated is guaranteed to detect it. If a test pattern cannot be generated using TEA, the target fault is untestable given the timing exception paths in the design and the existing simulation environment. Compared to the existing simulation-based approach, using TEA can generate a more effective test set, improving test coverage, test pattern count, and the total ATPG run time significantly.

The paper presents a novel test data compression scheme. This low-silicon-area solution builds on the isometric compression paradigm, but makes it more flexible, elevates encoding efficiency to values unachievable through any conventional type of sequential compression, and ensures high test coverage due to programmable selection of full toggle scan chains. The presented approach follows from a fundamental observation that only a few specified positions in test cubes are necessary to detect faults, while the remaining ones have alternative sites. Such test cubes are used to form circular test templates which synergistically control a decompressor and guide ATPG to find assignments yielding highly compressible test cubes. A redesigned decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. Experimental results obtained for large industrial designs confirm superiority of the proposed scheme over state-of-the-art techniques and are reported herein.

This paper presents a novel scan-based design for test (DFT) paradigm. Compared with conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage or allows applying a much larger number of vectors within the same time interval. An equally important factor is the toggling activity during test-with this scheme, it remains similar to that of the mission mode. Several techniques are introduced that allow integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.

This paper presents a novel scan-based DFT paradigm. Compared to conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage, or allows applying much larger number of vectors within the same time interval. An equally important factor is the power dissipated during test - with the new scheme it remains similar to that of the mission mode. Several techniques are introduced that allow easy integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. Experimental results obtained for large and complex industrial ASIC designs illustrate feasibility of the proposed test schemes and are reported herein.

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

New methods are proposed to guide line justification and fault propagation in test generation procedures to derive compact test sets. Experiments on several industrial designs yielded, on average, 24% reduction in test set sizes.

In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs

A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns increase the ability to detect unmodeled defects. The proposed method can be used with any test generation procedure to improve the effectiveness of the tests in detecting unmodeled defects. Experimental results on several industrial designs show the effectiveness of defect aware tests. We also propose a measure to estimate the effectiveness of given test sets in detecting unmodeled defects.

This paper describes a fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss Jordan elimination method.

This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.

The paper introduces a new non-adaptive fault diagnosis technique for scan-based designs. The proposed scheme guarantees accurate and time-efficient identification of failing scan cells based on results of a convolutional test response compaction.

This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. A convolutional compactor can be easily configured into a MISR that preserves most of these properties. Experimental results demonstrate the efficiency of compaction for several industrial circuits.

This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic decision ordering, conflict driven recursive learning and conflict learning. An important feature shared by all these techniques is that they are triggered by the occurrence of a conflict in the generation of tests. Hence, they are not active all the time nor for all the faults. This feature allows the ATPG system that uses these techniques to resolve hard-to-resolve faults with far fewer backtracks and leaves the system as efficient as before in the absence of conflicts. We have incorporated these techniques into a commercial D-algorithm based ATPG tool. The experimental results on full scan versions of ITC'99 benchmark circuits demonstrate an improvement of the ATPG system both in the number of aborted faults and in test generation time.

In this work, a new and effective procedure, called REDI, to efficiently identify redundant single stuck-at faults in combinational logic circuits is proposed. The method is fault oriented and uses sensitizability of partial paths to determine redundant faults. It uses only implications and hence may not determine all the redundant faults of a circuit. However, experimental results presented on benchmark circuits show that the procedure identifies nearly all the redundant faults in most of the benchmark circuits. The key features of REDI that make it efficient are: partial path sensitization, blockage learning, dynamic branch ordering and fault grouping. Experimental results on benchmark circuits demonstrate the efficiency of the proposed procedure in identifying redundant faults in combinational logic circuits.