Building oscillator-based computing systems with emerging nano-device technologies has become a promising solution for unconventional computing tasks like computer vision and pattern recognition. However, simulation and analysis of these computing systems is both time and compute intensive due to the nonlinearity of new devices and the complex behavior of coupled oscillators. In order to speed up the simulation of coupled oscillator systems, we propose a simplified phase model to perform phase and frequency synchronization prediction based on a synthesis of earlier models. Our model can predict the frequency-locking behavior with several orders of magnitude speedup compared to direct evaluation, enabling the effective and efficient simulation of the large numbers of oscillators required for practical computing systems. We demonstrate the oscillator-based computing paradigm with three applications, pattern matching, convolution, and image segmentation. The simulation with these models are respectively sped up by factors of 780, 300, and 1120 in our tests.

Design automation (DA) is at a historical moment where it has a chance - after mathematics, statistics, and computer science - to establish itself as the fourth universal approach with widespread applications in a variety of scientific, engineering, and economic domains. We start by outlining some of the most important research contributions and industrial applications of the design automation; we identify key conceptual DA techniques and describe how they interact to form synthesis and analysis flows. Next, we discuss the most attractive emerging and pending DA domains by analyzing several recent technologies, applications, and conceptual trends. Our emphasis is not just on the most challenging research or the most lucrative application areas but also on the technological trends relevant to DA. Furthermore, we elaborate on the types of new DA techniques and tools that are required for further fundamental progress and improved practical relevance. In order to provide a balanced picture of DA, we also identify the most pronounced dangers in false starts and false research in DA. Finally, we briefly discuss the need for a DA educational reform and community social reorganization that are beneficial for rapid and impactful research and development contributions.

The human vision system understands and interprets complex scenes for a variety of visual tasks in real-time while consuming less than 20 Watts of power. The holistic design of artificial vision systems that will approach and eventually exceed the capabilities of human vision systems is a grand challenge. The design of such a system needs advances in multiple disciplines. This paper focuses on advances needed in the computational fabric and provides an overview of a new-genre of architectures inspired by advances in both the understanding of the visual cortex and the emergence of devices with new mechanisms for state computations.

Weakly coupled oscillators have shown promise as a computational building block that exploits the power of emerging low power high density nano-devices such as spin torque oscillators and vanadium oxide oscillators. In this paper, we develop a new analytic phase model as well as a circuit simulation to show how clusters and arrays of coupled oscillators can be inserted into three different stages of an image processing pipeline and provide comparable image recognition performance to traditional methods.

We discuss the opportunities of performing associative processing based on the phase locking of coupled oscillators. The use of coupled oscillators, rather than Boolean logic, provides for implementations using emerging nano-technology such as magnetic spin torque oscillators and resonant body transistor oscillators, which each have the potential of lower energy operations and higher density scaling than traditional CMOS solutions.

In this paper we will identify those aspects of the concurrent computing landscape that have changed since the 1980's and how those changes might impact the efficacy of parallel computing as we move from single- to multi- to many- and to massive numbers of processing cores.

Using random graphs, we address the need for non-local communication channels in emerging nanotechnology interconnection structures. In this model, a grid of √N × √N processing elements are connected by non-local wires, which are fabricated as a post processing self-assembly step by electro-chemical migration of functionalized carbon nanotubes. We show that under reasonable assumptions, 80% of the cells can be connected into a single spanning tree with only N wires deposited randomly across the surface of the substrate.

"Lightweight hierarchical error control coding (LHECC)" is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for high-performance chip-to-chip and on-chip interconnects. LHECC is designed such that its corresponding encoder and decoder logic may be tightly integrated into compact, high-speed, and low-latency I/O interfaces. LHECC operates over a new channel technology called multi-bit differential signaling (MBDS). MBDS channels utilize a physical-layer channel code called "N choose M (nCm)" encoding, where each channel is restricted to a symbol set such that half of the bits in each symbol are set to one. These symbol sets have properties that are utilized by LHECC to achieve error correction capability while requiring low or zero relative information overhead. In addition, these codes may be designed such that the latency and size of the corresponding decoders are tightly bounded. The effectiveness of these codes is demonstrated by modeling error behavior of MBDS interconnects over a range of transmission rates and noise characteristics

This paper describes a novel approach to the problem of model order reduction (MOR) of very large nonlinear systems. We consider the behavior of a dynamic nonlinear system as having two fundamental characteristics: a global behavioral "envelope" that describes major transformations to the state of the system under external stimuli and a local behavior that describes small perturbation responses. The nonlinear low order envelope function is generated by using the remainders from the coalescence of projection bases taken through a space-state sample. A behavioral model can then be expressed as the superposition of these two descriptions, operating according to the input stimuli and the current state value. The global behavior describes major transformations to the state of the system under external stimuli and the local behavior describes small perturbation responses. Local effects are captured by regions through a set of linear projections to a reduced state-space while global effects are captured by examining the non-commonalty among these projections. These "remainders" are used to build a modulation function that will generate the required dynamic changes in the common linear projection. The advantage of the envelope representation for strongly nonlinear systems is that it simplifies the complexity of the model into a two-part problem. Depending on the complexity or cost of the behavioral separation procedure, it can be repeated recursively

We present our system-level co-simulation environment for mixed domain microsystems. The environment provides synchronization and co-simulation between the Chatoyant MOEMS (micro-electro mechanical systems) simulator and ModelTech ModelSim. By using shared memory IPC (inter-process communication) and PDES (parallel discrete event simulation) techniques, we achieve two orders of magnitude speedup over standard pipe/socket communication.

Summary and Conclusions-This paper presents four models for optimizing the reliability of embedded systems considering both software and hardware reliability under cost constraints, and one model to optimize system cost under multiple reliability constraints. Previously, most optimization models have been developed for hardware-only or software-only systems by assuming the hardware, if any, has perfect reliability. In addition, they assume that failures for each hardware or software unit are statistically independent. In other words, none of the existing optimization models were developed for embedded systems (hardware and software) with failure dependencies. For our work, each of our models is suitable for a distinct set of conditions or situations. The first four models maximize reliability while meeting cost constraints, and the fifth model minimizes system cost under multiple reliability constraints. This is the first time that optimization of these kinds of models has been performed on this type of system. We demonstrate and validate our models for an embedded system with multiple applications sharing multiple resources. We use a Simulated Annealing optimization algorithm to demonstrate our system reliability optimization techniques for distributed systems, because of its flexibility for various problem types with various constraints. It is efficient, and provides satisfactory optimization results while meeting difficult-to-satisfy constraints.

We present a component-based multi-level mixed-signal design and simulation environment for microsystems spanning the domains of electronics, mechanics, and optics. The environment provides a solution to the problem of accurate modeling and simulation of multi-domain devices at the system level. This is achieved by partitioning the system into components that are modeled by analytic expressions. These expressions are reduced via linearization into regions of operation for each element of the component and solved with modified nodal analysis in the frequency domain, which guarantees convergence. Feedback among components is managed by a discrete event simulator sending composite signals between components. For electrical, and mechanical components, interaction is via physical connectivity while optical signals are modeled using complex scalar wavefronts, providing the accuracy necessary to model micro-optical components. Simulation speed vs. simulation accuracy can be tuned by controlling the granularity of the regions of operation of the devices, sample density of the optical wavefronts, or the time steps of the discrete event simulator. The methodology is specifically optimized for loosely coupled systems of complex components such as are found in multi-domain microsystems.

As designers become more aggressive in introducing optical components to micro-systems, rigorous optical models are required for system-level simulation tools. Common optical modeling techniques and approximations are not valid for most optical micro-systems, and those techniques that provide accurate simulation are computationally slow. In this paper, we introduce an angular frequency optical propagation technique that greatly reduces computation time while achieving the accuracy of a full scalar formulation. We present simulations of a diffractive optical MEM grating light valve to show the advantages of this optical propagation method and the integration of the technique into a system-level multi-domain CAD tool.

Chatoyant models free-space opto-electronic components and systems and performs simulations and analyses that allow designers to make informed system level trade-offs.Recently, the use of MEM bulk and surface micro-machining technology has enabled the fabrication of micro-optical-mechanical systems.This paper presents our models for diffractive optics and new analysis techniques which extend Chatoyant to support optical MEMS design.We show these features in the simulation of two optical MEM systems.

We present a robust datapath allocation method that is flexible enough to handle constraints imposed by a variety of target architectures. Key features of this method are its ability to handle accurate modeling of datapath units and the simultaneous optimization of direct objective functions. The proposed method consists of a new binding model construction scheme and an optimization technique based on simulated annealing. To illustrate the flexibility of this method, two datapath allocation procedures have been developed for two problem enviroments: (1) a procedure that incorporates interconnection area and delay estimates, where floor-planning is tightly integrated into datapath allocation; and (2) a procedure that handles registers, register files, and multiport memories for data storage, as well as random and linear topologies for interconnection architectures. Results from these two applications show our method produces competitive designs for benchmark circuits, as well as being flexible enough to be used for a variety of different domains.

As the complexity of circuit designs grows, designers look toward formal verification to achieve better test overage for validating complex designs. However, this approach is inherently computationally intensive, and hence, only small designs can be verified using this method. To achieve better performance, model abstraction is necessary. Model abstraction reduces the number of states necessary to perform formal verification while maintaining the functionality of the original model with respect to the specifications to be verified. As a result, model abstraction enables large designs to be formally verified. In this paper, we describe three methods for model abstraction based on semantics extraction from user models to improve the performance of formal verification tools.

There is growing interest in studying the possibility of reconfigurable architectures as replacements for general purpose computing for certain application domains. Reconfigurable systems can take advantage of deep computational pipelines, perform concurrent execution and are inherently data flow in nature. Furthermore, these systems have the capability of 'on the fly' reconfiguration of all or portions of the hardware to represent all the functionality required to complete the execution of an application. However, these architectures suffer from slow run time reconfiguration (RTR) due to the fact that the configuration memory resides off-chip and hence requires high access latency. This disadvantage limits the system performance and the application domain in which reconfigurable systems could prove effective. To overcome slow RTR, recent approaches include on-chip configuration memory to cache the next possible configurations. This approach trades off die area for fast RTR which diminishes the processing power of the reconfigurable processor. The high cost of adding configuration cache, up to 50% of the die area, would considerably increase the number of hardware reconfigurations required compared to architectures without on-chip cache. This paper presents an alternative reconfigurable architecture which overcomes these limitations by exploiting high bandwidth optical channels. We develop a performance model to analyze and compare the performance of cache based RTR architectures, optical based RTR architectures and hybrid optical-cache based RTR architectures.

This paper presents a system capable of static and dynamic simulationsof heterogeneous opto-electronic systems. It is capable ofmodeling Gaussian optical signal propagation with mechanicaltolerancing at the system level. We present results which demonstratethe system's ability to predict the effects of various componentparameters, such as detector geometry, and system levelparameters, such as alignment tolerances, on system performance.

The authors argue in favor of the presumed commit protocol by proposing two new presumed commit variants that significantly reduce the cost of logging activities associated with the original presumed commit protocol. Furthermore, for read-only transactions, they apply their unsolicited update-vote optimization and show that the cost associated with this type of transactions is the same in both presumed commit and presumed abort protocols, thus, nullifying the basis for the argument that favors the presumed abort protocol. This is especially important for modern distributed environments which are characterized by high reliability and high probability of transactions being committed rather than aborted.

Transient signal analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points and on I/sub DD/ switching transients on the supply rails. We show that it is possible to identify defective devices by analyzing the transient signals produced at test points on paths not sensitized from the defect site. The small signal variations produced at these test points are analyzed in the frequency domain. Correlation analysis shows a high degree of correlation in these signals across the outputs of defect-free devices. We use regression analysis to show the absence of correlation across the outputs of bridging and open drain defective devices.

A novel approach to testing CMOS digital circuits is presented that is based on an analysis of I/sub DD/ switching transients on the supply rails and voltage transients at selected test points. We present simulation and hardware experiments which show distinguishable characteristics between the transient waveforms of defective and non-defective devices. These variations are shown to exist for CMOS open drain and bridging defects, located both on and off of a sensitized path.

Abstract | This paper presents a methodology for au-tomating the evaluation of partial designs using black-box testing techniques. This methodology generates black-box evaluation tests using a novel semantic graph data model to maintain the relationships between the related design and requirements data. We demonstrate the utility of this technique by using the relationship information to auto-matically generate and run functionality tests of partial designs against the related requirements. I.

We present a novel technique for datapath allocation, which incorporates interconnection area and delay estimates based on dynamic floorplanning. In this approach, datapath area is minimized by minimizing the number of wires, routing tracks, and multiplexers, while performance is optimized by minimizing wire length. The simultaneous optimization of these physical cost metrics allows the system to explore realistic design solutions.

Modern computer buses are typically organized by the three functions of data transfer, addressing, and arbitration/control. In this paper we present a fiber-based bus design which provides optical solutions for each of these functions. The design includes an all-optical addressing system, based on coincident pulse addressing, which eliminates the latency contribution and bandwidth limitation associated with electronic address decoding. The control system uses time-of-flight relationships between a priority chain and a feedback waveguide to implement fully distributed asynchronous and self-timed bus arbitration.>

An approach to the automatic generation of schematic diagrams from circuit descriptions is presented. The heuristics that make up the system are based on two principles of schematics readability: functional identification and traceability. SPAR's generation process is broken into five distinct phases: partitioning the netlist, placement of components on the page, global routing, local routing, and the addition of I/O modules. All phases of the generation process use a two-dimensional space management technique based on virtual tile spaces. The global router is guided by a cost function consisting of both congestion and wirelength estimates. The local router uses a constraint-propagation technique to optimize the traceability of lines through congested areas. The data structures and algorithms used allow the system to support incremental additions to the schematic without complete regeneration. A technique for evaluating the quality of schematic drawings is described and applied to the present results.>

In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the need to verify that existing digital components will interact correctly when placed together in a system. The system can also be used in the case of verifying specifications of unimplemented components. 1

Optical waveguides allow for enhanced bandwidth, loosened loading constraints and large physical distribution of computing resources. Moreover, optics enjoy a unique property that is not shared with electronics, namely the unidirectional propagation of signals. It is this property that is exploited in this paper to increase the effective bandwidth of optical buses. Specifically, a space-multiplexing technique for pipelined messages on optical buses is introduced and analysed. It is shown that pipelined buses support arbitrary routeing permutations in synchronous systems with only linear hardware complexity. Further, a bus arbitration protocol which extends the technique to asynchronous systems is presented. The pipelining of control and data signals represents a significant departure from the conventional exclusive access discipline which characterises bus-interconnected multiprocessors. By relaxing the exclusive access requirement, space multiplexing can support the design of large-scale, distributed, tightly coupled multiprocessor systems.

We propose a method for implementing “the election process” - finding an extrema of values computed in a multiprocessor network. It operates in an average time less than Log2(N), for a network of size N. It requires a single register, memory cell, or global buss into which all the processors can attempt to write, with the success of one guaranteed; and from which they may all read, in parallel. A second method is given which guarantees termination in O(Log2(MAX)) steps.