Demo Data from VLDB 2026 / reviewers in the wild / expert
Nafea Bishara
dblp:82/5656 · also Nafea Bshara
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2024
0009-0000-7696-6563ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 77% Interconnection networks and networks-on-chip · 23% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.8 | 1 | 2024 | AWS Trainium: The Journey for Designing and Optimization Full Stack ML Hardware · ASPLOS (3) 2024 |
Compilers and program optimization
accelerator compilation |
0.2 | 1 | 2024 | AWS Trainium: The Journey for Designing and Optimization Full Stack ML Hardware · ASPLOS (3) 2024 |
Interconnection networks and networks-on-chip › die-to-die interconnect
inter-chip communication |
0.2 | 1 | 2024 | AWS Trainium: The Journey for Designing and Optimization Full Stack ML Hardware · ASPLOS (3) 2024 |
Methods — techniques the papers use, named apart from their topics
hardware-software co-design · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | AWS Trainium: The Journey for Designing and Optimization Full Stack ML HardwareabstractMachine learning accelerators present a unique set of design challenges across chip architecture, instruction set, server design, compiler, and both inter- and intra-chip connectivity. With AWS Trainium, we've utilized AWS's end-to-end ownership from chip to server, network, compilers, and runtime tools to collaboratively design and optimize across all layers, emphasizing simplicity and ease of use. This talk will illustrate the design principles, tradeoffs, and lessons learned during the development of three generations of AWS ML products, from conceptualization to placing systems in the hands of AWS customers. Nafea Bishara |
ASPLOS (3) | 1 |