True Random Number Generator (TRNG) is indispensable in cryptographic algorithms and protocols, and the quality of randomness directly influences the security of cryptographic applications. Multiple theoretical or offline entropy estimation methods have been proposed to evaluate the security of TRNGs, while their ideal assumptions commonly cannot be satisfied due to the perturbation of operating conditions at runtime, which makes it difficult to achieve sufficient entropy for the output of TRNGs in practice. Moreover, the output bitrate of TRNG is another fundamental concern during TRNG practical applications, while popular elementary oscillator-based structure commonly has relatively low output bitrate due to the inherent low sensitivity of entropy extraction to jitter (source of randomness). In this paper, we aim to design a TRNG satisfying both practical security (i.e., on-chip entropy assurance) and high output bitrate simultaneously. In particular, an improved stochastic model and a measurement method are established to quantify the entropy of coherent sampling based TRNG. Moreover, an on-chip entropy assurance module is provided to realize the robustness of the proposed design under various operating conditions. We implement the proposed TRNG in a simulation platform and ASIC chips (with SMIC 130 nm CMOS technology). Experimental results indicate that the generated data has sufficient entropy ($\geq 0.999$per bit) under various operating conditions. In addition, all the output can pass the NIST SP800-22 and AIS 31 statistical tests with an output bitrate of 4.2 Mbps, which is equivalent to 2 orders of magnitude faster than that of the elementary oscillator-based TRNG.

Random numbers are essential for communications security, as they are widely employed as secret keys and other critical parameters of cryptographic algorithms. The Linux random number generator (LRNG) is the most popular open-source software-based random number generator (RNG). The security of LRNG is influenced by the overall design, especially the quality of entropy sources. Therefore, it is necessary to assess and quantify the quality of the entropy sources which contribute the main randomness to RNGs. In this paper, we perform an empirical study on the quality of entropy sources in LRNG with Linux kernel 5.6, and provide the following two findings. We first analyze two important entropy sources: jiffies and cycles, and propose a method to predict jiffies by cycles with high accuracy. The results indicate that, the jiffies can be correctly predicted thus contain almost no entropy in the condition of knowing cycles. The other important finding is the failure of interrupt cycles during system boot. The lower bits of cycles caused by interrupts contain little entropy, which is contrary to our traditional cognition that lower bits have more entropy. We believe these findings are of great significance to improve the efficiency and security of the RNG design on software platforms.

Mobile devices have been widely used to deploy security-sensitive applications such as mobile payments, mobile offices etc. SM2 digital signature technology is critical in these applications to provide the protection including identity authentication, data integrity, action non-repudiation. Since mobile devices are prone to being stolen or lost, several server-aided SM2 cooperative signature schemes have been proposed for the mobile scenario. However, existing solutions could not well fit the high-concurrency scenario which needs lightweight computation and communication complexity, especially for the server sides. In this paper, we propose a SM2 cooperative signature algorithm (SM2-CSA) for the high-concurrency scenario, which involves only one-time client-server interaction and one elliptic curve addition operation on the server side in the signing procedure. Theoretical analysis and practical tests shows that SM2-CSA can provide better computation and communication efficiency compared with existing schemes without compromising the security.

True random number generator (TRNG) as one essential hardware primitive is widely used in cryptography, Monte Carlo simulation, and gambling. To evaluate the security of TRNG, the entropy of the TRNG’s output is usually estimated by the stochastic model in theory or measured off-chip after fabrication. However, the sufficiency of entropy is difficult to be guaranteed in practice due to the facts: 1) the inaccuracy of the model-based jitter measurement method; 2) the variations of the chip manufacturing process and operating environments (such as supply voltage and temperature); and 3) malicious attacks. In this work, we design a novel TRNG architecture with on-chip entropy assurance to properly solve practical security problems. In the design, we propose an on-chip entropy estimator for measuring independent jitter to quantify true randomness, which enables continuous monitoring of TRNG at runtime. Furthermore, with the cooperation of the proposed on-chip entropy estimator and a rational self-adaptive mechanism, the designed TRNG can steadily generate bitstreams with sufficient entropy (≥ 0.999 per bit) against PVT variations. We implement the TRNG architecture in FPGAs with different technology nodes (45 and 65 nm) and SMIC 130 nm chips. Experimental results validate that the designed TRNG has an excellent performance in terms of technology independence and environmental robustness. The generated bitstreams pass the NIST SP800-22 and Diehard statistical test suites successfully without any post-processing.

Kyber is a promising candidate in post-quantum cryptography standardization process. In this paper, we propose a targeted optimization strategy and implement a processor for Kyber on FPGAs. By merging the operations, we cut off 29.4% clock cycles for Kyber512 and 33.3% for Kyber1024 compared with the textbook implementations. We utilize Gentlemen-Sande (GS) butterfly to optimize the Number-Theoretic Transform (NTT) implementation. The bottleneck of memory access is broken taking advantage of a dual-column sequential scheme. We further propose a pipeline architecture for better performance. The optimizations help the processor achieve 31684 NTT operations per second using only 477 LUTs, 237 FFs and 1 DSP. Our strategy is at least 3x more efficient than the state-of-the-art module for NTT with a similar security level.

Random number generator (RNG) is a fundamental and important cryptographic element, which has made an outstanding contribution to guaranteeing the network and communication security of cryptographic applications in the Internet age. In reality, if the random number used cannot provide sufficient randomness (unpredictability) as expected, these cryptographic applications are vulnerable to security threats and cause system crashes. Min-entropy is one of the approaches that are usually employed to quantify the unpredictability. The NIST Special Publication 800-90B adopts the concept of min-entropy in the design of its statistical entropy estimation methods, and the predictive model-based estimators added in the second draft of this standard effectively improve the overall capability of the test suite. However, these predictors have problems on limited application scope and high computational complexity, e.g., they have shortfalls in evaluating random numbers with long dependence and multivariate due to the huge time complexity (i.e., high-order polynomial time complexity). Fortunately, there has been increasing attention to using neural networks to model and forecast time series, and random numbers are also a type of time series. In our work, we propose several new and efficient approaches for min-entropy estimation by using neural network technologies and design a novel execution strategy for the proposed entropy estimation to make it applicable to the validation of both stationary and nonstationary sources. Compared with the 90B’s predictors officially published in 2018, the experimental results on various simulated and real-world data sources demonstrate that our predictors have a better performance on the accuracy, scope of applicability, and execution efficiency. The average execution efficiency of our predictors can be up to 10 times higher than that of the 90B’s for 10 6 sample size with different sample spaces. Furthermore, when the sample space is over 2 2 and the sample size is over 10 8 , the 90B’s predictors cannot give estimated results. Instead, our predictors can still provide accurate results. Copyright© 2019 John Wiley & Sons, Ltd.

True random number generators (TRNGs) are widely used in cryptographic systems, and their security is the base of many cryptographic algorithms and protocols. At present, entropy estimation based on a stochastic model is a well-recommended approach to evaluate the security of a specific TRNG structure. Besides, the generation speed is also an important property for TRNGs. For this purpose, an analog-to-digital converter (ADC) can be employed to sample the noisy signal to achieve high bit rate. However, no research focuses on the entropy estimation on the basis of the stochastic model toward ADC sampling. In this paper, we propose an entropy estimation for the ADC sampling-based TRNG through extending an existing model. In particular, we present an equivalent model to estimate the entropy of any single bit in the converted sample obtained by the ADC sampling. Furthermore, we propose a method of the entropy estimation for the multi-bit ADC output, which provides the lower bound of the entropy. By conducting simulations and hardware experiments on this type of TRNG, we confirm the correctness of the proposed entropy estimation theory. The prototype chip is fabricated in the SMIC 65-nm process, and the consumed power is 34 mW. The random bit sequences compatible with the AIS 31 standard are generated at a speed of 132.3 Mb/s. The sequences are able to pass the rigorous statistical test suites, including NIST SP 800-22, Diehard, and TestU01 (containing the Big Crush test), after simple post-processing at a bit rate of around 33 Mb/s.

The randomness of random number generators (RNGs) significantly influences the security of cryptographic systems. Although RNGs are allowed to adopt in practical systems only after strict analysis and security evaluation, the randomness of generated sequences may degrade due to aging effects of electronic devices, change of temperature and humidity, or even malicious attacks. Therefore, before the generated sequence being used (as a secret key or any other critical cryptography parameter), it is necessary to execute the on-the-fly statistical randomness test (on-the-fly test) on the candidate sequence to ensure the security. On-the-fly test should be finished efficiently; otherwise, it would impact the cryptographic systems' performance. In this paper, we propose a scheme to optimize the efficiency of randomness test suites, that is, provide an optimized order of the tests in the test suite, so that an unqualified sequence can be rejected as early as possible. We apply this optimization scheme on the NIST test suite (SP 800-22) [1] as an instance. Experimental results of 128- and 256- bit sequence, demonstrate that the optimized efficiency approximates to the theoretical optimum and the scheme can be quickly implemented.