The discretization error in MOSFET device simulation caused by a coarse grid is discussed. Delaunay and Voronoi discretization grids are used to demonstrate the discretization error. It is possible to clarify the discretization error by using these geometrically complementary grids. An error caused by a coarse grid in the subthreshold region originates from an inaccurate rectangular integral of the carrier density. For the Delaunay grid, the calculated inversion carrier density for a coarse grid is overestimated. In contrast, for the Voronoi grid, the inversion carrier density is underestimated. The equations for estimating the error in the subthreshold region are proposed. In the strong inversion region, the error for the Delaunay grid is smaller than the error in the subthreshold region. On the other hand, for the Voronoi grid, the error is large, even in the strong inversion region. The error for the Voronoi grid in the strong inversion region is caused by a quasi-capacitance originating from discretization.>

A two-dimensional (2-D) capacitance simulator for ultra-large-scale integrated (ULSI) circuits using an improved boundary-element method (BEM) is described. The capacitance simulator was linked with a topography/process simulator to estimate the distributed capacitances of complex structures based on actual processes. The utilization of a linear discontinuous element as the shape function is proposed in order to deal with multiregional problems by BEM. Other techniques employed in the simulation program, which enable precise calculation within practical CPU time, are also described. The calculated capacitances show good agreement with the experimental results.>

An examination is made of discretization methods for the two-dimensional current continuity equation used in device simulation. The authors have introduced the Baliga-Patankar discretization scheme to a device simulator for the first time and compared this scheme with the popular Scharfetter-Gummel scheme by using silicon n/sup +/-p diode current-voltage characteristics. Test computation reveals that the two schemes result in a 16% difference in the current values for 1.5 V of forward bias and a two-dimensional n/sup +/-p diode structure. The Baliga-Patankar scheme is rather insensitive to mesh, compared with the Scharfetter-Gummel scheme. On the other hand, the two schemes result in the same current-voltage characteristics for a one-dimensional diode structure. These results originate from the one-dimensional nature of the Scharfetter-Gummel scheme for drift dominant flow. The Baliga-Patankar scheme is robust for the two-dimensional current flow case, since this scheme defines a current density vector within each element.>