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Peter Nitezki

dblp:83/2948 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 35% Parallel and multicore computing · 22% Storage systems · 22%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › dataflow architecture
dataflow machine		 0.011989
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine · ISCA 1989
Parallel and multicore computing
data parallelism		 0.011989
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine · ISCA 1989
High-performance computing › parallel numerical algorithms
parallel signal processing		 0.011989
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine · ISCA 1989
Storage systems
signal processing		 0.011989
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine · ISCA 1989
Processor architecture and microarchitecture
dataflow architecture		 0.011989
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine · ISCA 1989
Processor architecture and microarchitecture › dataflow architecture
static dataflow		 0.011989
Exploiting Data Parallelism in Signal Processing on a Data Flow Machine · ISCA 1989
YearPublicationVenuePosition
1989 Exploiting Data Parallelism in Signal Processing on a Data Flow Machine
abstract
This paper will show that the massive data parallelism inherent to most signal processing tasks may be easily mapped onto the parallel structure of a data flow machine. A special system called STRUCTFLOW has been designed to optimize the static data flow model for hardware efficiency and low latency. The same abstractions from the general purpose data flow model that lead to a quasi systolic operation of the processing elements make explicit flow control of the data tokens as they pass through the arcs of the flow graph obsolete. We will describe the architecture of the system and discuss the restrictions on the structure of the flow graphs.
Peter Nitezki
 ISCA1