As ultra-large-scale integrated circuits continue to evolve, advanced packaging has become a promising approach to boost system performance, especially in high-performance computing applications. To support heterogeneous integration, multiple chiplets are integrated via large-area silicon interposers. However, due to reticle size limitations, interposer lithography requires multi-reticle stitching, which introduces high manufacturing costs and alignment-induced yield degradation. In this paper, we propose CIT-R3, a reticle-reuse-driven router that formulates routing and reticle reuse as a differentiable optimization problem. Additionally, a graph-patching algorithm is applied to enforce layout consistency across reused reticle regions. Experimental results on multi-chiplet benchmarks demonstrate significant reticle reuse improvements with minimal routing cost overhead.

With the slowdown of Moore’s Law, conventional monolithic chip architectures face challenges such as excessive die sizes and prohibitive manufacturing costs. Consequently, chiplets have emerged as a pivotal technology in the post-Moore era, attracting significant attention from both academia and industry. Multi-chiplet systems offer compelling advantages over monolithic ones, including enhanced integration density, reduced cost, and shortened time-to-market. However, realizing these benefits necessitates design flows capable of optimizing parameters across logical, physical, and circuit layers, which introduces substantial design complexity. Numerous design automation technologies have been proposed to address these challenges. This article provides a comprehensive overview of related advancements, categorizing chiplet design methodologies into two primary types: (i) top-down flows disintegrating existing hardware designs into chiplets and subsequently reintegrating them into multi-chiplet systems, and (ii) bottom-up flows combining existing chiplets into multi-chiplet systems based on user applications. This article begins by introducing foundational concepts, technical characteristics, and evaluation models relevant to multi-chiplet systems. We then systematically summarize the problem formulations, design spaces, and optimization techniques associated with top-down and bottom-up design flows. Finally, we discuss key challenges and potential future research directions in chiplet design automation, aimed at further harnessing the potential of chiplet-based integration.

As the number of chiplets in 2.5D IC continues to increase, existing chiplet placement method faces two main challenges: (1) the combinatorial explosion in the search space, and (2) the difficulty of achieving global optimization through iterativing chiplet and terminal placement. To tackle these challenges, we develop an efficient analytical RDL chiplet-terminal co-placement algorithm, to ensure simultaneous placement of chiplets and terminals. Our algorithm employs RDL chiplet-terminal co-placement in three stages: analytical global placement, legalization, and bump-terminal assignment, to achieve high-quality placement results that comply with design rules. Experimental results demonstrate that our algorithm reduces average wirelength by 31% compared to prior work for the common testcases, with a maximum speedup of up to 6500× in testcases with more than 10 chiplets.

Attribute-Specific Fashion Retrieval (ASFR) focuses on retrieving images based on fine-grained, attribute-specific criteria rather than naive global visual similarity, enabling more precise and interpretable search results. Existing ASFR methods ideally assume that all attribute semantics are in-domain distributions of the training datasets. However, realistic scenarios are generally more complex and naturally contain unseen attribute information, often resulting in ungeneralizable retrieval outcomes. In this paper, we take the first step to address the new and challenging open-world ASFR setting, which involves handling diverse and practical attributes instead of relying solely on predefined attribute sets in closed-world scenarios. Specifically, to comprehend unseen attributes, we propose a novel LLM-based Commonsense Knowledge Infusion (CoKi) framework that integrates commonsense knowledge as complementary context into attribute representations using a Large Language Model (LLM). By infusing such LLM-based commonsense knowledge through descriptive contexts, our method enables robust semantic enrichment and effective generalization to unseen attributes. Additionally, we introduce a modality-switchable prompt and an imputation mechanism to ensure model robustness across diverse input configurations by dynamically adapting to missing modalities. Extensive experiments demonstrate that our approach not only achieves state-of-the-art in-domain retrieval performance but also significantly enhances adaptability to unseen attributes and cross-domain generalization, establishing a new benchmark for fine-grained fashion retrieval in open-world scenarios. Our source code is publicly available at https://github.com/HuiGuanLab/CoKi.

Attribute-specific fashion retrieval (ASFR) is a challenging information retrieval task, which has attracted increasing attention in recent years. Different from traditional fashion retrieval which mainly focuses on optimizing holistic similarity, the ASFR task concentrates on attribute-specific similarity, resulting in more fine-grained and interpretable retrieval results. As the attribute-specific similarity typically corresponds to the specific subtle regions of images, we propose a Region-to-Patch Framework (RPF) that consists of a region-aware branch and a patch-aware branch to extract fine-grained attribute-related visual features for precise retrieval in a coarse-to-fine manner. In particular, the region-aware branch is first to be utilized to locate the potential regions related to the semantic of the given attribute. Then, considering that the located region is coarse and still contains the background visual contents, the patch-aware branch is proposed to capture patch-wise attribute-related details from the previous amplified region. Such a hybrid architecture strikes a proper balance between region localization and feature extraction. Besides, different from previous works that solely focus on discriminating the attribute-relevant foreground visual features, we argue that the attribute-irrelevant background features are also crucial for distinguishing the detailed visual contexts in a contrastive manner. Therefore, a novel E-InfoNCE loss based on the foreground and background representations is further proposed to improve the discrimination of attribute-specific representation. Extensive experiments on three datasets demonstrate the effectiveness of our proposed framework, and also show a decent generalization of our RPF on out-of-domain fashion images. Our source code is available at https://github.com/HuiGuanLab/RPF.

This paper proposes a new class of cellular automata, twi-layer couple cellular automata (TLCCA), with specific application to pseudorandom number generation. TLCCA consists of two layer each of which is a one dimensional CA. Two different rules are selected in the lower-layer CA on account of hybrid CA had more complex behavior. The upper-layer CA is divided into two parts. These two parts have a novel neighbourhood, which called couple-structure neighbourhood. By this neighbourhood, two parts in upper layer interplay with each other. ENT test suites are adopted to test the randomness of PRNG. In order to find a stable PRNG, Entropy, chi-square and serial correlation coefficient and their variability need to be considered. So a multi-objectives optimization algorithm is proposed. The results of experiment indicate that the TLCCA PRNG can obtain credible random number using no less than 48 cells. The merits of TLCCA PRNG are simpler structure, higher efficiency and better robusticity.

Evolvable Hardware(EHW) has been proposed as a promising technology for adaptive systems in last few years. However, in practical applications, evolutionary algorithms(EAs) often need numerous generations to search a new solution. In general, a mistaken system is damaged if it cannot restore in time, so the inefficiency problem has become an obstacle of developing adaptive and evolvable hardware. This paper analyzes how those three factors as genotype, algorithm, and methodology affect the efficiency of the EAs, as well as to what extent of their influence respectively, then proposes parallel and recursive decomposition (PRD) as a new decomposition strategy to accelerate the adaptation process from methodology perspective. Finally, some adaptive combination logical circuits are implemented on Xilinx Virtex-II Pro (XC2VP20) FPGA. The results demonstrate that PRD has more improvement on adaptation speed than some previous strategies.