In SoC, key infrastructure/backbone flows are distributed across many IPs and involve tight firmware and hardware interaction. Examples include resets, power management, security, and more. Traditional hardware validation techniques are no-longer adequate for such flows, due to the short time-to-market requirements, in particular, for mobile devices. In this paper, we articulate the challenges and discuss a few solution directions that are being pursued in this space at Intel.

In current SoCs, key infrastructure capabilities are distributed across many components and involve tight software, firmware, and hardware interaction. Examples include resets, power management, security, and more. The architectural complexity of these features often results in specification errors that when found quite late in the product life cycle are very costly to fix. This means that we have to find ways to analyze the architectural specification and not only the implementation. To address these issues, we describe a framework called iPave that supports the following capabilities: (1) A common, formal system-level specification serving as a contract between different design teams; (2) Specification analysis with focus on cross-component assumptions and dependencies; and (3) A method to reuse the specification as a global checker to assure that the implementation is compliant with the specification across all validation platforms (simulation, emulation, silicon). At the front end of this framework we have an intuitive visual formalism, iFlow, which makes it easy for architects to specify system-level protocols, while at the back end we have a new logical formalism, called Logic Sequence Diagrams (LSDs), which enables formal compliance checking across different validation platforms.

Intel's move towards the SoC paradigm comes with a compelling requirement for shorter time-to-market. To address that, we need to make both pre and post silicon validation more efficient. In this paper we focus on post-si functional validation, which consumes an increasing share of the overall product development timeline. We present a coherent Pre-to-Post workflow that aims to improve productivity of post-si validation and debug by proper investment in design for debug/validation (DFx) and in test development during pre-si stages. In this workflow, a central transactions and events definition repository serves as the backbone across pre-Si and post-Si activities. The transaction spec guides DFx work in pre-Si as well as test suite preparation in order to make the post-Si validation work productive. Usage of micro-architectural events and transactions raises the level of abstraction, and can help in getting better productivy, manageability, reusability, and less error prone Post-Si validation work.

Symbolic execution has long been a staple technique for formal hardware verification. Its application to software requires methods for dealing with software specific complexities. In this paper we elaborate methods for the efficient symbolic simulation of embedded software; some methods are new, others are improvements of existing methods. Using these techniques we have been able to symbolically execute real life microcode of thousands of lines, allowing formal methods to become an integral part of microcode validation in Intel Corporation.

We describe a general approach for defining new temporal specification languages, and adopting existing languages, for SystemC. We define the concept of "underlying trace" describing the execution of a SystemC model, and then define a set of important primitive assertions about the states in the trace. Our framework not only provides additional expressive power for making atomic assertions, but also provides very fine control over the temporal resolution of the language. Using the primitives defined here as clock expression allows sampling at different levels, from transaction-level to the level of individual statements. The advantage of our approach is that it defines important SystemC properties that have been overlooked previously, and also provides a uniform mechanism for specifying the sampling rate of temporal languages.

The ever-growing complexity of Intel® CPUs, together with shortened time-to-market requirements, poses significant challenges for pre-silicon logic verification. To address the increasing verification gap, major improvements to verification practices are required. In Merom, the Intel® Core^{TM} 2 Duo microprocessor, we integrated Formal Verification (FV) with Dynamic Verification (DV) such that FV was also practiced by non-FV experts and replaced some traditional, simulation-based verification activities. This led to both higher productivity and better quality compared to previous projects. In this paper we report on the integration we used, including two examples, results, and future directions.