VLDB 2026 Research / reviewers in the wild / expert
Brian K. Bray
dblp:83/740
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 1992
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 76% Processor architecture and microarchitecture · 24% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache |
0.0 | 3 | 1992 | The effect of page allocation on caches · MICRO 1992 Translation hint buffers to reduce access time of physically-addressed instruction caches · MICRO 1992 Strategies for Branch Target Buffers · MICRO 1991 |
Memory systems › cache › CPU cache
instruction cache |
0.0 | 2 | 1992 | Translation hint buffers to reduce access time of physically-addressed instruction caches · MICRO 1992 Strategies for Branch Target Buffers · MICRO 1991 |
Memory systems › memory management › virtual memory
address translation |
0.0 | 1 | 1992 | Translation hint buffers to reduce access time of physically-addressed instruction caches · MICRO 1992 |
Memory systems › memory management › memory allocation
page allocation |
0.0 | 1 | 1992 | The effect of page allocation on caches · MICRO 1992 |
Processor architecture and microarchitecture
branch prediction |
0.0 | 1 | 1991 | Strategies for Branch Target Buffers · MICRO 1991 |
Processor architecture and microarchitecture › branch prediction
branch target buffer |
0.0 | 1 | 1991 | Strategies for Branch Target Buffers · MICRO 1991 |
Operating systems › resource management
memory management |
0.0 | 1 | 1992 | The effect of page allocation on caches · MICRO 1992 |
Operating systems › resource management › memory management
page allocation |
0.0 | 1 | 1992 | The effect of page allocation on caches · MICRO 1992 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1992 | Translation hint buffers to reduce access time of physically-addressed instruction caches
Brian K. Bray, Michael J. Flynn |
MICRO | 1 |
| 1992 | The effect of page allocation on caches
William L. Lynch, Brian K. Bray, Michael J. Flynn |
MICRO | 2 |
| 1991 | Strategies for Branch Target BuffersabstractAchieving high instruction issue rates depends on the ability to dynamically predict branches. We compare two schemes for dynamic branch prediction: a separate branch target buffer and an instruction cache based branch target buffer. For instruction caches of 4KB and greater, instruction cache based branch prediction performance is a strong function of line size, and a weak function of instruction cache size. An instruction cache based branch target buffer with a line size of 8 (or 4) instructions performs about as well as a separate branch target buffer structure which has 64 (or 256, respectively) entries. Software can rearrange basic blocks in a procedure to reduce the number of taken branches, thus reducing the amount of branch prediction hardware needed. With software assistance, predicting all branches as not branching performs as well as a 4 entry branch target buffer without assistance, and a 4 entry branch target buffer with assistance performs as well as a 32 entry branch target buffer without assistance. The instruction cache based branch target buffer also benefits from the software, but only for line sizes of more than 4 instructions. Brian K. Bray, Michael J. Flynn |
MICRO | 1 |