A DSP based methodology to generate compensative stimuli is proposed to remove the parasitic effects in analog test buses. Experiments, using HSPICE simulation, show that the differences between stimuli and ideal signal are less then 1% with only 64 sample points.

A parasitic effect removal methodology is proposed to handle the large parasitic effects in analog testability buses. The removal is done by an on-chip test generation technique and an intrinsic response extraction algorithm. On-chip test generation creates test signals on-chip to avoid the parasitic effects of the test application bus. The intrinsic response extraction cross-checks and cancels the parasitic effects of both test application and response observation paths. The tests using both SPICE simulation and MNABST-1 P1149.4 test chip reveal that the proposed algorthm can not only remove the parasitic effects of the test buses but also tolerate test signal variations. Furthermore, it is robust enough to handle loud environmental noise and the nonlinearity of the switching devices.

This paper proposes an all digital on-chip bus delay and crosstalk measurement methodology. A diagnosis procedure is derived to distinguish the delay faults in drivers, receivers, and wires. The crosstalk profile is plotted by monitoring the changes in delay with the presence of the crosstalk. The distinguished features include all digital design and low hardware overhead. The SPICE simulation results prove the feasibility of the methodology.

A DSP based test methodology is proposed to remove the parasitic and crosstalk effects, the two major drawbacks when using the analog buses. Experiments, using SPICE simulation and real measurement data show a significant improvement over the direct measurement.

The removal of the parasitic effects is an emerging issue in the implementation of the IEEE standard 1149.4 analog test buses. For this, this paper defines the intrinsic response and derives an extraction algorithm. The intrinsic response is defined as the response of the circuit being tested by an ideal input signal without the parasitic effect. A deconvolution process is proposed to extract the intrinsic response from the response contaminated by the parasitic effects. The test results using SPICE simulation data show that the intrinsic responses remain the same regardless of the differences in the parasitic effects and the variations in the test signals. The proposed methodology is further tested in the real measurement using the MNABST-1 test chip designed by Matsushita/Panasonic and provided by 1149.4 Working Group. The test results show that the intrinsic response has an improvement of 15.4 dB in signal-to-noise ratio as compared to the direct measurement. It also extends the test frequency range by an order of magnitude. Both tests reassert that the intrinsic response is independent of parasitic effects and input signal variation. They also show that the proposed extraction algorithm is robust enough to handle not only the parasitic effects but also the noise in the real measurement environment.

In this paper an analog metrology and test stimulus selection guidelines are proposed based on the frequency domain analysis of the stimulus and the CUT. To show the feasibility, a 4th order leapfrog filter and a DSP deconvolution operation are used as the test vehicle. The experimental results on the real measured data show that the increase in observation periods can effectively compensate the increase in the environment noise.

This paper presents a metrology to extend P1149.4 from external component testing to internal module measurement. A series of experiment has been conducted to verify that the metrology is able to tolerate parasitic effects and test signal variation. As compare to the direct measurement, the metrology achieves an improvement of 14 dB in measurement SNR. Furthermore, it also extends the frequency range by one order.

The interconnect BIST is achieved by the on-line polling for the composite vectors that contain the encoded information, for the test generation and response evaluation on selective drivers and receivers to adapt to the changing configuration.

Signal reconstruction reconstructs a multiple period low-rate sampled waveform into a one-period high-rate sampled waveform. With which, we are able to provide sufficient samples of analog signals for DSP based testing using on-chip ADCs. Test results show that a 128-sample-per-period waveform can be reconstructed from a 2.4 samples per period waveform sampled by a 20 MHz 8-bit ADC.

An intrinsic response extraction algorithm is derived and implemented to remove the parasitic effects in P1149.4 analog measurement. The methodology is tested on and verified by SPICE simulation results and real measurement data.

In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module.