Error tolerance techniques are widely used to protect processor pipelines from variation induced timing errors. In this paper, we propose two standard cell library tuning techniques to optimize error tolerant processor pipelines for power and area savings. The design utilizes positive slack available in the pipeline stages and re-distributes it to the preceding error-prone critical paths using slack balancing flip-flops. Library pruning analyses the power and area metrics of the flip-flop cells to derive a power efficient subset of the original library. We use statistical sigma corner libraries to replace the critical flip-flop fan-in cone for further power optimization. Results show that the proposed library tuning techniques provide power reductions of 47% and area reductions of 2.8% in the employed execute stage module of a processor pipeline.

Energy efficient semiconductor chips are in high demand to cater the needs of today's smart products.Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance.Existing run time resilience techniques are not cost effective due to the additional circuits involved.In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths.We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings.Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design.Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.

There is much focus on timing error resilience for the speed critical paths of processors. In the context of growing parameter variations with technology scaling and voltage scaling, resilience helps to ensure functional correctness. Moreover it allows the chip to stretch its operating voltage and frequency beyond the conventional limits to meet the demand for high performance and low power. Conventionally, timing error resilience is achieved through variation tolerant circuitry at the cost of undesirable power, area and throughput overheads. Such overheads are aggravated by the presence of large number of critical timing paths in the design. In this paper, we propose a slack-aware timing margin redistribution technique for error resilience using time borrowing error avoidance flip-flops (EAFFs) while minimizing overheads. The proposed algorithm designs the processor critical paths ground up by inserting EAFFs at places where positive slack is available in the subsequent fan-out stage. Experiment results on an industrial processor design show that a timing margin improvement of 11% of the clock period can be achieved on 64% of the critical paths and a 55% timing margin on 45% of the critical paths without any throughput degradation. The area and power overheads of the additional flip-flops are 0.2% and 5.4%, respectively.

Digital pollution is emerging as an overwhelming threat to the Internet, whose ubiquitous connectivity conversely cultivates the widespread outbreaks of such dirt. Considerable amount of human efforts and network resources are wasted at a little cost of the few polluters. To prevent flooding of the contamination, classical string matching schemes and their variants can be used to detect these patterns for removal. The speed of detection is crucial to this application. In this paper, we propose a novel pattern detection technique based on the decision tree induction to seek for significant improvement over the classical schemes. According to the intrinsic of the pattern, the tree is sprouted adaptively to minimize the number of symbols in the data stream needs to be examined. This allows a unique order to inspect the symbols in a strategic way optimized contextually, as opposed to the fixed order followed by the other schemes. Performance study indicates our approach achieves the speed-up of five or more over the best competitors.

Efficient similarity search in large string databases requires effective index support. Since long strings have each numerous substrings of arbitrary length, the effective index designs are of great challenge. The existing solution, namely MRS [T. Kahveci et al., (2001)], employs a low-cost lower bound function to sieve out the most similar candidates from the majority of unlikely database substrings. Therefore, only very small portions of string databases require the expensive true edit distance computation to finalize the query. A significant savings in overall query processing cost can be realized by the filtration feature of lower bound functions. In this paper, we seek to improve MRS to its full potential. Specifically, we propose a very simple method that exchanges the roles of database strings and query string in the original MRS design. Despite simplicity, our solution can further improve the query performance by 10 times in terms of disk page accesses while using only half of the original index's size.