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Saul Levy

dblp:84/1737 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 47% Interconnection networks and networks-on-chip · 47% Performance modeling and evaluation · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network topology
hierarchical interconnection network
0.021992
Efficient Hierarchical Interconnection for Multiprocessor Systems · SC 1992
Design and analysis of efficient hierarchical interconnection networks · SC 1991
Parallel and multicore computing
multiprocessor system
0.021992
Efficient Hierarchical Interconnection for Multiprocessor Systems · SC 1992
Design and analysis of efficient hierarchical interconnection networks · SC 1991
Parallel and multicore computing › parallel architecture
message-passing architecture
0.011991
Design and analysis of efficient hierarchical interconnection networks · SC 1991
Performance modeling and evaluation › network performance analysis
network performance modeling
0.011992
Efficient Hierarchical Interconnection for Multiprocessor Systems · SC 1992
Interconnection networks and networks-on-chip
communication locality
0.011991
Design and analysis of efficient hierarchical interconnection networks · SC 1991

Methods — techniques the papers use, named apart from their topics

unbuffered network model · 0.0design parameter optimization · 0.0buffered network model · 0.0traffic density analysis · 0.0hierarchical network design · 0.0
YearPublicationVenuePosition
1992 Efficient Hierarchical Interconnection for Multiprocessor Systems
abstract
The authors present a novel approach to the design of a class of hierarchical interconnection networks for multiprocessor systems. This approach, based on an architecture providing separate networks for each level, gives a general and flexible way to construct efficient hierarchical networks. The performance and cost-effectiveness of the resulting networks are analyzed and compared in detail, using both unbuffered and buffered network models. It is shown that, if the design parameters are determined based on the degree of locality, the cost-effectiveness of a hierarchical network can be significantly improved. In addition, the authors investigate how to construct a cost-effectiveness hierarchical network by determining appropriate design parameters. Two associated algorithms are developed for this purpose.>
Sizheng Wei, Saul Levy
SC2
1991 Design and analysis of efficient hierarchical interconnection networks
abstract
Hierarchical interconnection networks exploit locality in communication to reduce the number of links in the networks.In this paper, we propose a cla8s of general hierarchical interconnection network8 for message-passing architectures.We show that a new approach to design, choosing the appropriate number of interface nodes, considerably reduces not only intercluster trafic density but also intracluster trafic density.
Sizheng Wei, Saul Levy
SC2