The notion of logic proximity bridge (LPB) is introduced. An algorithm to enumerate LPBs, using only the logic net-list, is discussed. Although no correlation exist between the LPB list and the realistic bridge list, LPB patterns are shown to compare very favorably with realistic bridge and n-detect patterns on several coverage metrics. This result points to the potential for LPB patterns as an alternative to both realistic bridge and n-detect patterns.

Traditionally, digital testing of integrated semiconductor circuits has focused on manufacturing defects. There is another class of failures that happens due to circuit marginalities. Circuit-marginality failures are on the rise due to shrinking process geometries, diminishing supply voltage, sharper signal-transition rates, and aggressive styles in circuit design. There are many different marginality issues that may render a circuit nonoperational. Capacitive cross coupling between interconnects is known to be a leading cause for marginality-related failures. In this paper, we present novel techniques to model and prioritize capacitive crosstalk faults. Experimental results are provided to show effectiveness of the proposed modeling technique on large industrial designs.

Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect-based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two-node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented.

Current bridge fault extraction techniques are limited by performance and capacity constraints. In this paper, we present a fast and accurate algorithm to extract and rank two-node bridges based on the computation of their weighted critical area. Experimental results showing the algorithm's performance are presented.

An impressive body of theoretical research to model the behavior of bridges exists. We take that a step further and describe an experiment to compute single cycle scan tests for bridges and evaluate them in silicon. Experimental data, on a high volume part, shows that by marginally increasing the static bridge fault coverage of realistic bridges, unique parts missed by a comprehensive set of stuck-at tests were detected. We believe that this is the first silicon data on the value of adding single cycle scan tests for bridges to the manufacturing flow.

Previously published work has pointed out that open defects are escaping test screens. To plug this hole, tests directed at nets susceptible to opens are required, and, therefore, nets susceptible to opens need to be identified. Opens caused by random particles have been modeled using weighted critical area (WCA) and have been previously studied. Here, we present a model that abstracts a class of systematic failure mechanisms that leads to open nets. An algorithm to calculate net scores using this model is presented. Experimental results on industrial designs show the algorithm to have reasonable performance.

Defect based testing is based on the premise that it is possible to extract high probability defects viz. bridges and opens using layout and defect data. We present a very efficient algorithm to extract two-node bridges from layout. Comparison results with a popular tool show that our algorithm is considerably faster and that it has higher capacity.

Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented.

State-transition-based method (STBM), a fast algorithm for computing leakage fault coverage of I/sub DDQ/ tests and selecting optimal I/sub DDQ/ measurement points, targeting leakage faults, is presented. Experimental results presented show that STBM outperforms all known algorithms for the same problems. A comparative study of leakage and pseudo-stuck-at fault models, the latter used by commercial tool vendors, show that the pseudo-stuck-at coverage values are very pessimistic.