Demo Data from VLDB 2026 / reviewers in the wild / expert
Totadri Jayasri
dblp:84/4450
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1976
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% Electronic design automation · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 1 | 1976 | An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words · IEEE Trans. Computers 1976 |
Processor architecture and microarchitecture
microprogramming |
0.0 | 1 | 1976 | An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words · IEEE Trans. Computers 1976 |
Methods — techniques the papers use, named apart from their topics
linear programming · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1976 | An Approach to Organizing Microinstructions which Minimizes the Width of Control Store WordsabstractThis paper suggests a new method for minimizing the width or bit dimension of control store words in microprogrammed digital computers. It is shown that any given problem can be formulated within the framework of linear programming and that there exists a lower limit CLB to the number of bits. The optimal grouping of subcommands which gives this minimal width is also readily obtainable. Totadri Jayasri, Dhruba Basu |
IEEE Trans. Computers | 1 |