Demo Data from VLDB 2026 / reviewers in the wild / expert
Shriram Kulkarni
dblp:84/506
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3Software engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 91% Processor architecture and microarchitecture · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 1 | 1998 | Digital circuit applications of resonant tunneling devices · Proc. IEEE 1998 |
Integrated circuit design › digital circuit design › logic design
logic circuits |
0.0 | 1 | 1998 | Digital circuit applications of resonant tunneling devices · Proc. IEEE 1998 |
Integrated circuit design › digital circuit design
multivalued logic circuit |
0.0 | 1 | 1998 | Digital circuit applications of resonant tunneling devices · Proc. IEEE 1998 |
Processor architecture and microarchitecture
pipelining |
0.0 | 1 | 1998 | Digital circuit applications of resonant tunneling devices · Proc. IEEE 1998 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2001 | A physical design tool for built-in self-repairable RAMsabstractIn this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs. Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder |
IEEE Trans. Very Large Scale Integr. Syst. | 2 |
| 2000 | A prototyping technique for large-scale RTD-CMOS circuitsabstractIn this paper we present a method for prototyping circuits designed using resonant-tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) devices that can enable us to realize large-scale digital circuits with negative differential-resistance (NDR) devices. Our method is based on designing CMOS circuits which can emulate the current-voltage (I-V) characteristics of RTDs. We demonstrate the effectiveness of our scheme by means of simulation and fabrication of an NDR shift register circuit. Mayukh Bhattacharya, Shriram Kulkarni, Alejandro F. González, Pinaki Mazumder |
ISCAS | 2 |
| 1999 | A Physical Design Tool for Built-in Self-Repairable Static RAMsabstractA novel physical design tool, BISRAMGEN, that generates layout geometries of parametrized built-in self-repairable SRAM modules, producing significant improvement in testability, reliability, production yield and manufacturing cost of ASICs and microprocessors with embedded RAMs, is presented. Kanad Chakraborty, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder |
DATE | 4 |
| 1998 | Digital circuit applications of resonant tunneling devicesabstractMany semiconductor quantum devices utilize a novel tunneling transport mechanism that allows picosecond device switching speeds. The negative differential resistance characteristic of these devices, achieved due to resonant tunneling, is also ideally suited for the design of highly compact, self-latching logic circuits. As a result, quantum device technology is a promising emerging alternative for high-performance very-large-scale-integration design. The bistable nature of the basic logic gates implemented using resonant tunneling devices has been utilized in the development of a gate-level pipelining technique, called nanopipelining, that significantly improves the throughput and speed of pipelined systems. The advent of multiple-peak resonant tunneling diodes provides a viable means for efficient design of multiple-valued circuits with decreased interconnect complexity and reduced device count as compared to multiple-valued circuits in conventional technologies. This paper details various circuit design accomplishments in the area of binary and multiple-valued logic using resonant tunneling diodes (RTD's) in conjunction with high-performance III-V devices such as heterojunction bipolar transistors (HBT's) and modulation doped field-effect transistors (MODFET's). New bistable logic families using RTD+HBT and RTD+MODFET gates are described that provide a single-gate, self-latching majority function in addition to basic NAND, NOR, and inverter gates. Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Jian Ping Sun, George I. Haddad |
Proc. IEEE | 2 |