Demo Data from VLDB 2026 / reviewers in the wild / expert
Darshan D. Thaker
dblp:84/618
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2008
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Emerging computing paradigms · 83% Memory systems · 9% Interconnection networks and networks-on-chip · 8% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Emerging computing paradigms
quantum computer architecture |
0.1 | 2 | 2006 | Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing · ISCA 2006 A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation · MICRO 2005 |
Emerging computing paradigms › quantum computer architecture
fault-tolerant quantum computing |
0.1 | 1 | 2005 | A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation · MICRO 2005 |
Memory systems › memory hierarchy
memory hierarchy design |
0.0 | 1 | 2006 | Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing · ISCA 2006 |
Methods — techniques the papers use, named apart from their topics
application and system analysis · 0.1quantum teleportation · 0.1quantum error correction · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | High-level interconnect model for the quantum logic array architectureabstractWe summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLA's logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shor's quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing. Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross, Isaac L. Chuang, Fred Chong |
ACM J. Emerg. Technol. Comput. Syst. | 2 |
| 2006 | A Realizable Distributed Ion-Trap Quantum Computer
Darshan D. Thaker, Tzvetan S. Metodi, Fred Chong |
HiPC | 1 |
| 2006 | Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum ComputingabstractThe assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The resulting architectures overcome the primary challenges of reliability and scalability at the cost of physically unacceptable system area. We find that by exploiting the natural serialization at both the application and the physical microarchitecture level of a quantum computer, we can reduce the area requirement while improving performance. In particular we present a scalable quantum architecture design that employs specialization of the system into memory and computational regions, each individually optimized to match hardware support to the available parallelism. Through careful application and system analysis, we find that our new architecture can yield up to a factor of thirteen savings in area due to specialization. In addition, by providing a memory hierarchy design for quantum computers, we can increase time performance by a factor of eight. This result brings us closer to the realization of a quantum processor that can solve meaningful problems Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cross, Isaac L. Chuang, Fred Chong |
ISCA | 1 |
| 2005 | A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and ComputationabstractRecent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into a scalable, fault-tolerant system that is also feasible. We propose a quantum logic array (QLA) microarchitecture that forms the foundation of such a system. The QLA focuses on the communication resources necessary to efficiently support fault-tolerant computations. We leverage the extensive groundwork in quantum error correction theory and provide analysis that shows that our system is both asymptotically and empirically fault tolerant. Specifically, we use the QLA to implement a hierarchical, array-based design and a logarithmic expense quantum-teleportation communication protocol. Our goal is to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum computing. Our work complements recent work by Balenseifer et al. (2005), which studies the software tool chain necessary to simplify development of quantum applications; here we focus on modeling a full-scale optimized microarchitecture for scalable computing. Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross |
MICRO | 2 |