This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a technique that enables the efficient loading of the x-masking data into the masking logic in a parallel fashion using the scan chains. A method for eliminating the requirement for dedicated mask control signals using automated test equipment timing flexibility is also presented. The proposed compactor is especially suited to multisite testing. Experiments with industrial designs show that the proposed compactor enables compaction ratios exceeding 200x.

Production test is a significant driver of semiconductor manufacturing cost. Test cost is highly influenced by the test concept of a product. This paper gives an overview over the test concept of a complex mobile phone SOC. The particular example is a highly integrated SOC for entry-level mobile phones. The SOC consists, besides digital processing units, of a variety of embedded M/S blocks, an embedded FM radio, and a complete RF transceiver for mobile communication. The paper describes the production test approaches for different groups of embedded circuitry, e.g. digital logic, mixed-signal, etc. Design-for-Test measures are briefly described. A breakdown of relative test times, proportional to production test cost, with respect to different groups of circuitry is presented. Limitations of existing test equipment and future challenges in order to further reduce test cost for complex SOCs are explained based on industrial implementation experience.

Technology and product ramp up suffers increasingly from systematic production defects. Diagnosis of scan test fail data plays an important role in yield enhancement as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production can lead to significant test time overhead. This paper presents a new on-chip architecture that evaluates scan test results and stores relevant scan diagnosis information on chip. Scan diagnosis data can be accessed after the scan test has finished with very little test time overhead. Moreover, the proposed technique is ATE independent. An implementation example, based on a state-of-the-art SoC device, is reported

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

This paper addresses delay test for SOC devices on low-cost testers. The case study focuses on the at-speed testing for a state-of the-art microcontroller device by using an on-chip high-speed clock generator. The experimental results show that the simple on-chip high-speed clock generator is not sufficient to reach both high fault coverage and acceptable pattern count. Meanwhile, at-speed test constraints, required to enable the delay test on low cost testers, have a significant impact on test generation results. DFT techniques to increase fault coverage and to reduce pattern count are discussed.