This paper introduces an ultra-low-power amplifier-less front-end architecture for amperometric electrochemical sensing. The proposed architecture can simultaneously regulate the potential difference between the required electrodes and perform current readout for an electrochemical sensor. A dual-side potentiostat regulation loop comprising dynamic latched comparators in conjunction with digital loop filters and current-steering DACs is proposed, with its detailed operation discussed in this paper. Implemented in a standard 180 nm CMOS process, this design achieves a current measurement range of 114.3 dB. It can operate over a wide range of sampling frequencies FS (100 Hz ~ 100 MHz) and supply voltages (1 V ~ 1.8 V). The whole interface IC consumes only 3.50 nA current at 1.2 V supply at a clock frequency of 1-kHz.

Wearable physiological monitoring systems increasingly require continuous, low-power sensing interfaces capable of seamless integration into flexible Internet of Things (IoT) platforms. Conventional architectures rely on analog-to-digital converter (ADC) based front-ends and rigid electronics, which elevate system power, increase design complexity, and limit textilelevel conformity. To address these restraints, this paper presents a self-driven, fully integrated resistance-to-frequency converter system for continuous, and low-power wearable physiological monitoring. The proposed architecture eliminates conventional analog-to-digital converters (ADCs) and high-gain amplification stages by directly converting resistive strain variations into a frequency-modulated signal. The system comprises a flexible carbon-PDMS-based flexible sensor, exhibiting a gauge factor of approximately 80. The fabricated resistive sensor is embedded in a Wheatstone bridge front-end, which drives a lowcomplexity BJT-based push-pull astable oscillator operating in the 1–3 kHz band with a sensitivity of 50 Hz/kΩ. The BJTbased oscillator leverages a hybrid RC–LC topology, where an integrated inductor (L1) enhances the quality factor from 5 to 15, reducing phase noise by over 15 dB and directly improving startup reliability and temperature stability. The overall system is realized on a flexible PCB with an integrated mini ATmega16U4 microcontroller for frequency counting and an nRF52840 Bluetooth module for wireless transmission. Experimental validation demonstrates robust tracking of respiratory and body movement patterns with sub-hertz resolution, mean absolute error below 0.8 breaths per minute, and motion repeatability error under 3%. The design achieves an ultra-low duty-cycled power consumption, with a time-averaged current of 75 μA, enabling extended time operation from a 90 mAh battery. Finally, the system is fully textile-integrated using hand-knitting technique, ensuring user conformity by retaining >98% of its baseline electrical performance after 20 gentle machine-wash cycles.

• Formulates malware classification as a Markov Decision Process with episodic feature acquisition, achieving superior performance across diverse datasets: 99.20% F1-score on Microsoft Big2015, 98.64% on BODMAS, and 85.07% on EMBER 2018 using reinforcement learning. • Demonstrates systematic superiority over traditional approaches through comprehensive ablation studies, where static feature selection methods exhibit severe performance degradation (up to 10.40% F1-score reduction) while D3QN maintains consistent improvements across all evaluation scenarios. • Validates robust transferability with 76.08% average recall on unseen EMBER 2024 malware variants across six diverse file formats, demonstrating 27.55% relative improvement over traditional methods and effective zero-day threat detection capabilities. • Introduces quantitative intelligence assessment framework proving strategic learning behavior with 62.5% categorical preference deviation from random baselines, 57.7% feature specialization, and autonomous discovery of domain-aligned cybersecurity patterns without explicit supervision. Traditional malware detection methods exhibit computational inefficiency due to exhaustive feature extraction requirements, creating accuracy-efficiency trade-offs that limit real-time deployment. We formulate malware classification as a Markov Decision Process with episodic feature acquisition and propose a Dueling Double Deep Q-Network (D3QN) framework for adaptive sequential feature selection. The agent learns to dynamically explore informative features per sample before terminating with classification decisions, optimizing both detection accuracy and computational cost through reinforcement learning. We evaluate our approach on Microsoft Big2015 (9-class, 1795 features), BODMAS and EMBER 2018 (binary, 2381 features) datasets. D3QN achieves 99.20%, 98.64%, and 85.07% F1-scores respectively while utilizing approximately 60 features on average, representing 96.6% and 97.5% dimensionality reduction compared to full feature sets. Comprehensive ablation studies across six feature selection methods demonstrate that traditional approaches suffer severe performance degradation (averaging 1.85-10.40% F1-score reduction) when constrained to comparable feature subsets, while D3QN maintains consistent improvements (+1.38% to +5.08%) across all evaluation scenarios. Cross-dataset transferability validation on EMBER 2024 demonstrates superior zero-day detection capabilities, achieving 76.08% average recall on unseen malware variants across diverse file formats–representing 27.55% relative improvement over traditional methods. Quantitative intelligence assessment reveals strategic learning behavior with 62.5% categorical preference deviation from random baselines and 57.7% feature specialization. The learned policies exhibit autonomous discovery of domain-aligned patterns, identifying structural anomaly indicators and behavioral signatures characteristic of cybersecurity expertise. Our results validate reinforcement learning-based sequential feature selection for malware classification, achieving superior accuracy with substantial computational reduction through learned adaptive policies that outperform static dimensionality reduction techniques across diverse threat landscapes.

As the demand for embedding edge intelligence in vision systems continues to grow, future image sensors must become smarter and capable of performing efficient on-chip computation. This paper presents a hardware-friendly computational CMOS image sensor (C2IS) that performs signed analog-domain multi-bit convolution directly within the pixel array to enable energy-efficient embedded vision. The proposed C2IS uses a compact two-transistor (2T) pixel—without in-pixel weight memory or capacitors—while maintaining a 43% fill factor. By leveraging programmable column link switches and shared CTIA+SS-ADC channels, the system supports up to eight programmable convolution kernels per frame without requiring intermediate SRAM or DAC for partial-sum storage. Fabricated in a standard 0.18$\mu $m CMOS process, the prototype achieves 1.5-2.0 TOPS/W performance (normalized to 1-bit), corresponding to 14–112 fps at 61.8–82.4$\mu $W total chip power. A vision system incorporating the proposed C2IS demonstrates validation accuracy of 96.7% for handwritten digit recognition and 94.2% for hand gesture recognition. These results confirm the feasibility of this approach for low-power, high-density feature extraction, making it well suited for next-generation edge AI applications.

This paper presents a technique to effectively reduce the number of conversion cycles of the 1st-order incremental delta-sigma data converter (IADC1). Typically, an IADC1 requires 2Ncycles to achieve N-bit resolution if using a sinc1filter for reconstruction. The proposed quantization-skip technique can effectively reduce the average conversion cycles and, therefore, the energy consumption of an IADC1. Specifically, during conversion, the quantizer output is predicted using the previous bitstream pattern to achieve automatic bitstream fill-in without analog domain operations. Behavioral level simulations show that this technique can reduce the conversion cycles by 24% on average (maximum reduction of ~50%) with little digital overhead.

Ambient light interference is a significant hurdle as it creates unwanted DC current in optical receivers used for visible light communication, infrared communication, etc., that face solar irradiance in the daytime or unwanted light sources such as bulbs at night. This paper presents a current mirror-based receiver topology. By introducing a current-to-voltage converter module, the receiver can handily remove the background interference. A prototype receiver is designed using a 180 nm CMOS process operating at a speed of 160 MHz. It can cancel up to 100 µA of DC background interference while maintaining a low power dissipation of 7 mW from a 1.8 V supply. Additionally, it achieves a transimpedance gain of 120 dBΩ and an input referred noise of 10 pA/ Hz.

Adder is a complex digital circuit because of its interconnectivity, which hinders fault detection and localization. This paper compares two approaches of fault localization in adders based on carry-free addition using signed digits (SD) representation and localized self-checking-full adders for ripple carry adders (RCA). The self-repairing SD adder approach requires computation with standard and shifted inputs toward left and right for fault localization. The resulting complexity caused by the shifting operation is unnecessary for the self-repairing RCA, which simultaneously achieves fault detection and localization. Moreover, the centralized checking mechanism of the SD adder results in system failure if the checker becomes faulty. However, in the case of self-repairing RCA, the failure of individual full adders will not create problems in the self-checking ability of other full adders owing to the distributed fault detection mechanism. It has been observed that the self-checking RCA implemented in FPGA is $\mathbf{6 2 \%}$ more area efficient than the self-checking signed digit adder in terms of LUTs.

A novel down-sampling filter named moving accumulative sign filter (MASF) is proposed for low-power down-sampling of large-scale binary and ternary data. Besides, the MASF has greatly circuit realization advantages than state-of-the-art cascaded-integrator-comb (CIC) filter, especially in the area of low-power design. The theory of MASF is proposed and introduced comprehensively, including the algorithm model, transfer function, and frequency response characteristics. The pipeline voting architecture is applied to the implementation of the MASF to improve the speed of data processing, which simplifies the circuit structure and reduce the power consumption. The MASF circuits of general application based on pipeline voting are designed for binary and ternary signals only using D flip-flop and logic gates. The area and power consumption of MASF are reduced by 86% and 88% compared with CIC filter under the same conditions on FPGA. What’s more, a hardware-friendly pooling algorithm named polar-pooling is proposed based on MASF for binary and ternary feature maps, which greatly reduces the time and space complexity of pooling. Compared with max-pooling and average-pooling, the processing time of polar-pooling is reduced by more than 75% for a$200\times 200$binary image. The two-stage MASF circuit for ternary signal processing is implemented at 40-nm CMOS process, compared with state-of-the-arts cascade-of-integrators filter which cascading two integrators, the normalized power consumption of proposed two-stage MASF circuit has 67% reduction and the area has 75% reduction.

Cyclic redundancy check (CRC) and Forward error correction (FEC) encoding are widely used in high-speed information transceiver systems such as PCIe, JESD204C and fiber-optic communications to detect or correct errors in data. Traditionally, the CRC and FEC encoding circuits in JESD204C are implemented independently of each other, which consumes a significant amount of hardware resources. Therefore, a high logic density CRC and FEC logic sharing (CFLS) encoding circuit for JESD204C controller is proposed in this paper, and the logic density of the encoding circuit is improved by sharing the registers and common encoding factor (CEF). Meanwhile, a straightforward critical path delay (CPD) calculation method was proposed to assess whether the data transmission delay satisfies the requirements of CFLS circuits. This method is derived in conjunction with the manipulation of the common factor matrix, thus reducing computational complexity. The CFLS encoding circuit proposed in this paper is verified with an FPGA platform, and the results show that the circuit can realize CRC and FEC function with a 21.96% reduction in hardware resources, compared to the traditional methods. The area of the JESD204C controller with CFLS encoding circuits is 0.09 mm2, by using a 40-nm CMOS process, and the power consumption is 24.66 mW according to the post-layout simulation.

Ultra-thin strain sensors have received vast attention due to their ultra-thin and ultra-soft skin-conformable nature with numerous applications in wearable electronics for soft robotics, health monitoring, and human-machine interfaces. With the most recent developments in printing technologies, printing electronics directly on ultra-thin substrates is now more beneficial comparing with the conventional lithographic based electronic fabrication techniques, as printing offers several unique benefits in terms of wide-ranging material processability, process simplification, rapidness, and lower costs. Here, we report an ultra-thin and high performance strain sensor based on metal/polymer composite films, fully fabricated by inkjet-printing on a biocompatible decal transfer substrate (thickness $\approx 1 \mu {\mathrm {m}}$). The sensor patches are consist of two inkjet printed layers i.e. a highly conductive metal bottom-layer made of silver nanoparticles and a polymer top-layer made of poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS). The sensor patches exhibit the average gauge factor (GF) of around 12, and stretchability of up to 10%, with excellent durability (stretch/release tests up to 500 cycles). As application demonstrations, the strain sensors are employed to monitor the subtle human muscle movements, demonstrating excellent performance. The results show that our ultra-thin strain sensors have broad applications in next-generation smart wearable electronics.

This paper presents a high-precision bandgap voltage reference (BGR) with high-order temperature compensation. The compensation signal is generated by using both strong-inversion MOSFETs and Bipolar Junction transistors (BJTs), which cancels the high-order nonlinear term$T\ln (T)$in the BJT base-emitter voltage (VBE), and thus a low temperature coefficient (TC) over a wide temperature range is achieved. The proposed BGR circuit is fabricated in a 0.18-$\mu \text{m}$CMOS process with an active area of$0.256 m{m^{2}}$and a max power consumption of 1.35 mW. A minimum TC of 0.706${\mathrm{ppm}}/{}^ \circ C$from$- 25\,\,{}^ \circ C$to 125${}^ \circ C$is achieved after an 8-bit resistance trimming. The line sensitivity is 0.0146%/V operating from 3.2 V to 3.7 V. The BGR achieves a power supply rejection (PSR) of −63.4 dB and a noise spectrum density of$0.92 ~\mu \text{V}/\sqrt {Hz} $at 10 Hz.

This paper introduces a broadband linear driver used in B-PLC system. The driver consists of two identical current-feedback amplifiers to realize a fully differential topology. A cross-current injection method between the noninverting and the inverting channels is proposed to reduce the even-order harmonics caused by the circuit mismatch. In addition, in order to increase the stability of the GBW to the changing load and maximize the bandwidth, a output stage implemented by a unit gain closed-loop amplifier is proposed to stabilize the open-loop gain of the overall circuit, meanwhile improve the linearity deteriorated by the crossover distortion. The proposed linear driver is fabricated in a SOI CBJT process and it can provide a maximum drive current of 500 mA under a 12-V power supply. The measurement results show that this linear driver is capable of driving a load of$50~\Omega $while achieving a output swing of$16~{V_{pp}}$with a second-order harmonic distortion (HD2) of −72 dBm and a third-order harmonic distortion (HD3) of −55 dBm. The bandwidth can reach 120 MHz. A complete in-system measurement also has been passed and the results show that the proposed driver chip can well meet the need of the B-PLC system.

Visible light communication (VLC) transceivers suffer from optical interference and ambient light saturation, which severely affect the reception of optical signals. In this paper, we discuss various techniques for the suppression of ambient light in electronic, optical, communication and wavelength domains with focus on VLC systems for vehicular communication. Designing transceivers for outdoor VLC systems is challenging due to the dynamic environment and the time-varying nature of interference from different types of ambient light sources. This is a unique study that addresses the problem of optical interference in multiple physical domains and offers qualitative insights in a systematic manner.

Recently, there has been a surge of interest in applying memristors to hardware implementations of deep neural networks due to various desirable properties of the memristor, such as nonvolativity, multivalue, and nanosize. Most existing neural network circuit designs, however, are based on generic frameworks that are not optimized for memristors. Furthermore, to the best of our knowledge, there are no existing efficient memristor-based implementations of complex neural network operators, such as deconvolutions and squeeze-and-excitation (SE) blocks, which are critical for achieving high accuracy in common medical image analysis applications, such as semantic segmentation. This article proposes convolution-kernel first (CKF), an efficient scheme for designing memristor-based fully convolutional neural networks (FCNs). Compared with existing neural network circuits, CKF enables effective parameter pruning, which significantly reduces circuit power consumption. Furthermore, CKF includes the novel, memristor-optimized implementations of deconvolution layers and SE blocks. Simulation results on real medical image segmentation tasks confirm that CKF obtains up to 56.2% reduction in terms of computations and 33.62-W reduction in terms of power consumption in the circuit after weight pruning while retaining high accuracy on the test set. Moreover, the pruning results can be applied directly to existing circuits without any modification for the corresponding system.

CMOS current readout is a critical circuit block for various applications like bio-sensing. This paper presents an overview of CMOS current readout techniques and analyze their merits and demerits, including noise floor, sensitivity, and achievable system bandwidth. Mainly, the practical applicability of individual technique/design for integrated low-noise bio-sensing applications is discussed. To present a thorough insight of the state-of-the-art, most recent and relevant articles published in the literature related to the current sensing interface are summarized and compared. The paper identified the primary DC current rejection schemes, where each approach and its limitations are discussed and shown that each system comes with its limits.

Soft wearable strain sensors having high sensitivity along with high deformability have been actively investigated. However, their facile and mass-production at a lower cost remains a challenge. This paper presents the rapid fabrication of soft resistive strain sensors by multi-nozzle electrohydrodynamic (EHD) inkjet printing technique. printing head comprises of five needles with discrete counter/ground electrodes is used for simultaneous printing of silver nanoparticle ink on prestrained thermoplastic polyurethane (TPU) substrate. By means of this approach, soft circuits with diverse working strain ranges are realized and tested. As an application, a soft strain sensor based on the multi-nozzle EHD printed circuit is employed for monitoring the human motion (finger bending), demonstrating the potential applications of these circuits in soft wearable electronic devices and soft human-machine interfaces.

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard$0.18~\mu \text{m}$CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes$1.53~\mu \text{W}$with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling.

In an 8B/10B mode giga-bit-per-second serial data transactions, the de-serialized data is sent to a comma detection and word alignment (CDWA) module to identify the word boundaries, which is a prerequisite in the high-speed transceivers such as PCIe, USB and JESD204B/C. In order to ensure that the comma code (/K/-code) can be correctly detected. Ten 10-bit comma detector cells are adopted in a typical CDWA module, which require a complex circuitry and an enormous power consumption. To overcome these limitations, a low-area and low-power CDWA circuit for JESD204B/C transceiver chip in 8B/10B mode has been proposed in this paper. The bit width of the detector cells can be truncated from 10 to 6 under the condition, that CDWA module can detect a complete comma code correctly. On one hand, the proposed CDWA module is verified with a FPGA development platform with the reduction of the hardware resources and power consumption to 31.72% and 20.11% respectively as compared to the typical structure available. On the other hand, a 10-Gbps transceiver chip with the proposed CDWA module is fabricated with a 55-nm CMOS process and the word alignment function of the proposed module is proved by the measurement results. The area of this transceiver chip including 2× transmitting links and 2× receiving links is 2.89 mm2, and the power consumption is 467.8 mW, under a maximum data transmission rate of 10 Gbps.

This paper presents the time-domain analysis of a fully differential incremental ΔΣ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1st- and 2nd-order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers.

One of the main challenges in establishing a robust visible light communication (VLC) link is to prevent optical interference produced by other light sources from corrupting the signal. Previous solutions aiming to solve this issue assume that the signal and optical noise are present in nonoverlapping frequency bands. Our design incorporates an innovative transceiver architecture for establishing a frequency-independent interference-tolerant VLC link. The transmitter exploits the polarization property of light to transmit differential signals over adjacent channels, and the receiver utilizes differential amplification in conjunction with polarization to reject any common-mode optical noise. Thus, we can reliably establish an interference tolerant VLC link for medium data rate applications.

“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

This paper presents a high sensitivity and high frame rate hydrogen ion image sensor in standard CMOS process for high accuracy and high throughput hydrogen ion monitoring. A novel ion-to-current-to-voltage sensing front-end using 2-transistor (2T) and a column capacitive transimpedance instrumentation amplifier (CTIA) enable high pixel density, high sensitivity and rapid response time. A column successive approximate register (SAR)-Single Slope (SS) dual-mode analog-to-digital converter (ADC) is employed as it outperforms SS ADC on quantization speed and power efficiency while occupies less chip area to be able to fit in a pixel column compared with SAR ADC. Due to the novel sensing front-end and dual-mode ADC employed, the proposed CMOS ion image sensor system achieves a simulated 191mV/pH sensitivity and 2219 fps frame rate.

The existing CMOS platforms monitor the bacterial growth using single mode sensor and the bacteria samples are prepared separately which cause unreliable sensing results and potential contamination. In this paper, we present a CMOS multi-sensor array features high sensitive hydrogen ion, optical sensing and temperature modulation capability for accurate on-chip bacterial growth monitoring. A novel high sensitive hydrogen ion sensor and image sensor are integrated with an in-pixel capacitive transimpedance instrumentation amplifier (CTIA) to achieve both pH and optical sensing functionalities. The temperature modulation for on-chip bacteria culturing is realized through temperature sensor, heater and control circuit. A column SAR-Single Slope dual-mode ADC is employed, considering a quantization speed, chip area compromise and its compatibility with correlative double sampling. A state-of-the-art pH sensitivity of 217mV/pH is achieved in simulation. The high sensitive and multi-sensing features also make this sensing platform a promising candidate for antibiotic study, DNA sequencing, etc.

Due to the aging effect and exposure to reactive gases, the response of gas sensors tends to deviate. This deviation in sensors' response is termed as drift. The drift of sensors is a challenging issue that limits the use of sensors over longer periods of time because the pattern recognition and classification systems fail to recognize the deviated response of sensors. To address this problem, this paper proposes the use of Recursive Feature Elimination (RFE) based Random Forests (RF) for compensation of small-scale drift in gas sensors. The proposed method is evaluated for the classification of six volatile compounds and is compared with multiple state-of-the-art classifiers and feature selection techniques using a benchmark dataset publicly available online. The results depict that the RF-RFE combination outperforms the other classifiers and feature selection techniques.

This paper investigates printing functional materials on diverse flexible substrates for rapid detection of volatile organic compounds (VOCs). Inkjet printing and doctor blade coating is performed for rapid manufacturing of the sensing devices. The three different substrates selected are polyethylene terephthalate (PET), cotton fabric and a common A4 type printing paper. The structural and morphological properties of the substrates are exploited to compare the detection of three different types of VOCs, such as acetone, ethanol and isopropanol. A silver (Ag) nanoparticles-based ink at suitable properties for inkjet printer is used for developing the interdigital electrodes. A nanocomposite of Carbon-based paste is applied as sensing layer. Geometrical parameters of the devices, materials, processing and sintering conditions are kept similar, to only explore the distinguished sensing capabilities based on the substrate materials. Two different concentrations i.e. 4 and 22 ppm (parts per million) of the representative VOCs are applied in the test chamber and corresponding chemoresistance values are recorded using a sourcemeter. The different resistance peak values and responses times are correlated with the type of substrates and a comparative study is performed based on the type of substrate. This research presents greater contribution in the field of large area, cost-effective and wearable VOCs sensors that are highly demanding both for industrial as well as environmental monitoring. Some of these VOCs are considered as potential bioanalytes, which can be used in the recognition of several chronic diseases using these wearable sensing devices.

This paper presents a chopper instrumentation amplifier design that employs a proposed amplifier slicing technique for offset reduction. In this scheme, the core amplifier is split into multiple identical slices. During operation, the offset polarity of these slices is firstly determined by employing the second-stage of the amplifier as a static comparator. Next, by using the polarity information, the amplifier slices are regrouped to achieve statistical offset suppression. A mathematical model is developed in this paper to estimate the effectiveness of this reduction scheme. The sliced amplifier structure also enables a scalable noise and bandwidth without adding extra analog components. Simulation results show that the proposed reduction scheme achieves a > 40 dB offset suppression and a noise efficiency factor (NEF) of 2.2. The circuit is implemented in a 0.18 μm standard CMOS technology for proof of concept and consumes 0.4 μA to 1 μA current from a 1.2 V supply to reach a noise level from 90 nV/√Hz to 31.8 nV/√Hz, respectively.

This paper presents the first end-to-end network for exemplar-based video colorization. The main challenge is to achieve temporal consistency while remaining faithful to the reference style. To address this issue, we introduce a recurrent framework that unifies the semantic correspondence and color propagation steps. Both steps allow a provided reference image to guide the colorization of every frame, thus reducing accumulated propagation errors. Video frames are colorized in sequence based on the colorization history, and its coherency is further enforced by the temporal consistency loss. All of these components, learned end-to-end, help produce realistic videos with good temporal stability. Experiments show our result is superior to the state-of-the-art methods both quantitatively and qualitatively.

A fully differential transimpedence amplifier (TIA) that serves as a receiver front-end for visible light communication (VLC) is proposed. The TIA incorporates an ambient light rejection circuit in the form of a floating active inductor (FAI) which can effectively bypass photocurrent (upto 50μA) and allows the subsequent transimpedence stage to only integrate the modulated photocurrent. This helps to avoid receiver saturation when exposed to excessive optical interference (i.e. large DC photocurrent) in outdoor environment of intelligent transport systems (ITS). Implemented in TSMC 0.18μm CMOS process, the proposed VLC receiver front-end consumes 220 μA bias current and exhibit transimpedence gain of 98dBΩ. Our design is aimed for VLC based receivers in intelligent transport systems by enabling active tracking between VLC transmitter and receiver using the same degree of polarization of light.

After a certain period of time, there is a change in response of the gas sensors, which is caused by drift. This change in response of the gas sensors causes deterioration which makes the artificial intelligence algorithms worthless for prediction. As the algorithms are trained on data without drift and once the effect of drift starts causing an error in prediction, the system needs re-calibration, which is a cumbersome process. Neural Networks (NN) are proved to have the capability of solving many complex problems in different fields. In this paper, an averaging Neural Network ensemble model is proposed to compensate the effect of drift in gas sensors and is tested for quantification of Industrial gases. The dataset used for validating the proposed model is a large scale experimental data, available online.

This paper investigates the bit-error probability of several color shift keying (CSK) constellations in a visible light communications (VLC) scenario with a camera-based receiver. A novel VLC communication constellation set, the extended circular CSK, is presented and analyzed. Its performance is compared to the CSK constellation described in the IEEE 802.15.7 standard, in addition to other constellations that were introduced previously, namely the geometric and circular CSK constellations. The bit-error rate (BER) of the proposed extended circular CSK constellation is studied. Simulation results show that the extended circular CSK significantly outperforms the other constellations and deserves further research attention in the future.

In this paper, we propose a lossy image compression algorithm called microshift. We employ an algorithm-hardware co-design methodology, yielding a hardware-friendly compression approach with low power consumption. In our method, the image is first micro-shifted, and then the sub-quantized values are further compressed. Two methods, FAST and MRF models, are proposed to recover the bitdepth by exploiting the spatial correlation of natural images. Both methods can decompress images progressively. On an average, our compression algorithm can compress images to 1.25-bits per pixel with a resulting quality that outperforms the state-of-the-art on-chip compression algorithms in both peak signal-to-noise ratio and structual similarity. Then, we propose a hardware architecture and implement the algorithm on an FPGA. The results on the ASIC design further validate the low-hardware complexity and high-power efficiency, showing that our method is promising, particularly for low-power wireless vision sensor networks.

This paper presents a smart system for large flow range measurement, consisting of a dual-mode MEMS flow sensor and the readout IC. During high flow rate (> 25 m/s), the output of the dual-mode sensor is directly digitized by a switched-capacitor incremental delta-sigma ADC with 12-bits resolution due to its large output amplitude. While in low flow rate, the sensor output is first amplified by a capacitively-coupled instrumentation amplifier (CCIA) before digitization. A comparator is employed to enable a dynamic switching between two operation modes based on the flow rate. The readout IC can handle a large input up to 800 mV and consumes a current as low as 114 μA. The simulation results show the measurement system achieves a maximum sensing flow rate of 73 m/s while contributes a maximum measurement error rate of 300 ppm which is considerably lower than the industry standard of 3%.

Incremental analog to digital converters (IADCs) are aimed at converting low frequency signals with high accuracy. The operational transconductance amplifiers (OTAs) used to implement the integrators are the dominant source of power consumption, since they must settle to a desired accuracy within a given clock period, by driving a capacitive load. Reducing the capacitor size correspondingly increases the thermal noise power which reduces the signal-to-noise ratio (SNR) of the ADC. In this paper, we introduce a capacitor scaling technique which exploits the uneven weightage of the IADC decimation filter on the output bit-stream of the IADC. The power consumption can be scaled down correspondingly but the noise power does not increase by the same extent, leading to greater energy efficiency. A second order feedforward IADC is simulated to demonstrate the idea, which achieves up to a 25% improvement in energy efficiency using the proposed scheme.

A CMOS gas-sensitive field-effect transistor (Gas-FET) is proposed for noninvasive diabetes detection. The Gas-FET was fabricated in the GlobalFoundries 0.18μm 1P6M process with a lateral control gate and a floating gate to set operating point and gas sensing sensitivity, respectively. ZnO nanorods were used as the sensing material and deposited on top of the chip using a hydrothermal process at 80°C. Room-temperature acetone sensing down to sub-ppm level is demonstrated to enable noninvasive diagnosis of diabetes in exhaled breath. A dual-mode integrated readout circuit is also proposed to improve the sensor gas discrimination ability through the acquisition of 2-dimensional information by every single Gas-FET sensor.

Recently, various image quality assessment (IQA) metrics based on gradient similarity have been developed. In this paper, we extend the work of gradient magnitude similarity deviation (GMSD) and propose a more efficient metric. First, a novel similarity index is proposed, which gives the flexibility to tune the masking parameter to more closely match the human vision system (HVS). Then, we propose a multi-scale GMSD method by incorporating scores of luminance distortion at different scales. Furthermore, a method for measuring chromatic distortions in YIQ color space based on our metric is proposed. The final IQA index, MS-GMSDc, is obtained by combining luminance and chrominance scores. Experimental results on four comprehensive datasets clearly show that, compared with 14 state-of-the-art IQA methods, our method achieves the best performance for both grayscale and chromatic image assessment.

In recent years, a large number of image retargeting methods have been proposed. Measuring their relative quality is of significant importance, and there is still room for improvement in the effectiveness of objective retargeted image quality assessment (RIQA) metrics. In this paper, we propose a registration based RIQA metric. First, we propose to calculate the flow map using an image registration method which involves SURF point matching and halfway domain optimization. Using the computed flow map and the source image, we propose an LGI metric which contains three factors: 1) local similarity which assesses the local aspect ratio change, edge directional similarity and flow smoothness; 2) global distortion which measures the appearance change of salient objects; 3) salient information loss. Comparing with other six metrics, our LGI metric correlates the best with subjective rankings on the RetargetMe dataset.

This paper presents an ultra-low-power low-noise Capacitively-coupled Chopper Instrumentation Amplifier (CCIA). A current-reuse telescopic topology in the first stage along with a recycling folded-cascode topology in the second stage consumes net bias current of 26μA with enhanced efficiency and achieves an input-referred noise power-spectral-density of 12.77nV/√Hz. The proposed CCIA is chopped at 50kHz to bring the input-referred offset around 6μV and flicker-noise corner around 400mHz. Implemented in chartered 0.18μm CMOS process and designed for Thermoresistive Micro Calorimetric Flow (TMCF) sensors, the reported work achieves an excellent Noise Efficiency Factor (NEF) of 2.5 which is the lowest ever reported NEF for such applications.

This paper presents a novel dual transduction gas sensor providing both resistance and mass modalities for single sensor gas identification. The proposed sensor relies on a configurable dual mode frequency/resistance readout circuit, which enables the use of a single conventional surface acoustic wave (SAW) device. Unlike prior works which all rely on custom-made gas sensors, the proposed sensor is based on off-the-shelf SAW devices, making it low cost and easy to implement. Reported results validate the functionality of the proposed dual transduction gas sensor. The introduction of control switches for the dual mode readout is shown to only deteriorate the phase noise performance of the SAW oscillator by 4 dBc/Hz at 10 MHz offset and not affect the low offset part. This demonstrates that the mass sensing resolution of the SAW device is not reduced while including the resistive sensing feature.

Incremental analog to digital converters (lADCs) are aimed at converting low frequency signals with high accuracy. However the use of high oversampling ratios (OSR) usually decreases the conversion speed making them energy inefficient. The first integrator also consumes a lot of power due to high settling requirements, if a single bit quantizer is used. This paper introduces a two step feedforward IADC using an asynchronous Successive Approximation Register (SAR) ADC as a multi-bit quantizer. The same SAR ADC is then used to convert the residue of the incremental conversion. The extended counting enables high conversion speed and the use of a multibit quantizer reduces settling requirements for the first integrator. As a result, high power efficiency is achieved. The ADC achieves a peak SNR of 88.6 dB within a Nyquist bandwidth of 2.5 kHz, with a power consumption of only 8.44 μW. The measured Waiden and Schreier FoMs are 74 fj/conv.-step and 173.3 dB, respectively.

A low-offset two-stage dynamic comparator has been proposed for parallel multi-channel processing. Low offset is achieved from two aspects: 1st-stage offset cancellation and 2nd-stage offset suppression. A fully dynamic offset cancellation scheme based on current auto-zeroing is adopted to effectively cancel out the 1st-stage offset. It features small area overhead and low energy consumption. For the 2nd-stage offset suppression, a high gain is designed for the 1st-stage dynamic amplifier by optimizing the overdrive voltage of input transistors. To maintain low offset performance across a wide range of input commonmode voltages, the overdrive voltage of the input pair is required to stay low. Therefore, a tail current source is employed for the 1st stage to ensure constant common-mode discharging current. As a result, the overdrive voltage can be stably kept low under various operation conditions. The proposed comparator has been designed in a standard CMOS 0.18 μm process. It operates under a supply voltage of 1.2 V at 10 MHz. Simulation results have verified the low-offset property of the comparator. The input-referred offset (1 σ) is reduced from 19.25 mV to 1.296 mV after cancellation and it remains constant with the input commonmode voltage changing from 0 V to 0.8 V. The offset is further reduced to 771 μV when the 2nd-stage input pair are enlarged by 4 times. At the same time, the energy consumption is increased from 147 fJ/Conv to 168 fJ/Conv.

A gas discrimination system is mainly made of two parts, the sensing part and the processing part. As an alternative solution to pure software or hardware implementation of the processing part of a gas identification system, this paper proposes a gas discrimination system and its implementation on the Zynq system on chip platform using hardware/software co-design approach. In addition, the recommended system uses principal component analysis for dimensionality reduction, binary decision tree for classification and a 4×4 in-house gas sensor array for sensing. Moreover, k-nearest neighbors classifier is also used and compared with decision tree. MATLAB is used for simulation and validation before the final implementation on the Zynq. Algorithms are implemented using high level synthesis and different optimization directives are applied. Hardware implementation results on the Zynq show that real-time performances can be achieved for proposed e-nose system using hardware/software co-design approach with a single ARM processor running at 667 MHz and the programmable logic running at 142 MHz.

A micro-power incremental delta-sigma (I-ΣS) ADC is presented. This ADC uses its decimation filter's output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18μm CMOS, the 0.12mm2 ADC consumes 2.16μW at a conversion speed of 85S/s, 15.3b resolution and -2/1.5LSB INL.

This paper proposes a hardware/software co-design approach using the Zynq platform for the implementation of an electronic nose (EN) system based on principal component analysis (PCA) as a dimensionality reduction technique and decision tree (DT) as a classification algorithm using a 4x4 in-house fabricated sensor. The system was successfully trained and simulated in MATLAB environment prior to the implementation on the Zynq platform. High level synthesis was carried out on the proposed designs using different optimization directives including loop unrolling, array partitioning and pipelining.

Analyzing the concentration of acetone in human breath constitutes a promising non-invasive means to diagnose the onset of diabetes, with acetone levels of at least 1.8ppm typically associated to individuals suffering from diabetes. In this paper, we report the performance of a hierarchical ZnO nanostructure gas sensor for acetone detection. The fabricated gas sensor can detect concentrations as low as 1ppm while operating at a comparatively lower temperature of 200°C. In addition, the proposed gas sensor can be fabricated on a silicon wafer using a MEMS process, making it thereby possible to fully integrate gas sensing and electronic circuitry on a single silicon chip.

In RF energy harvesting for wireless sensor network, due to the variation of the available RF power for individual node sensor, the conventional Dickson rectifier could not achieve the optimal harvesting efficiency in a wide available power range. In this work, a novel reconfigurable rectifier with adjustable conversion ratio is proposed without changing matching network. Based on this, a WLAN (2.4 GHz) RF energy harvesting system is proposed with the maximum power point tracking (MPPT). The entire system is implemented in an 180nm CMOS process. Post-layout HSPICE simulation results show that with MPPT, the reconfigurable rectifier achieves a high energy harvesting efficiency for a wide available power range and is configured with 3.3x response time reduction when compared with the existing reconfigurable rectifier to cater for the frequent changing RF power.

Planned Sensor Distortion (PSD) is a compression method that quantizes shifted signal with low bit depth. In this paper, we analyze the dynamic range loss issue in the PSD algorithm and propose two novel methods to overcome this issue: a blocked PSD, which divides the image into sub-blocks that adapt to pixel values, and an auto-reset PSD, which utilizes Markov property to recover a high dynamic range image from the modulo image. Simulation on a 3-bit depth image of indoor environment shows PSNR of 35.7dB and 35.0dB respectively after reconstruction using our algorithms. Thereafter, two different implementations for PSD are proposed, introducing shifts at either reset phase or readout phase. These circuits are then extended to be compatible with our proposed algorithms. Finally, simulation results using 0.18um GlobalFoundries process validate our designs. Spontaneous power optimization of ADC and transmission, hardware friendly feature, and the ability of high quality imaging make our compression method promising.

An analog-to-information converter (AIC) enables information quantization instead of signal quantization, which can reduce both quantization efforts and data bandwidth. Therefore, an AIC will relax data processing and transmission burden and improve overall power efficiency, making it attractive for wireless vision sensor networks. In this paper, we propose a background subtraction based column-parallel AIC for motion-triggered vision sensors. It features low-power and robust background subtraction for motion extraction as well as efficient information quantization. The AIC is implemented by integrating background subtraction with a successive-approximation-register and single-lope (SAR-SS) hybrid ADC using a new architecture. Targeting at scene interpretation applications, 6-bit background and 8-bit foreground are adopted. Simulation results show that vision data bandwidth and ADC power are reduced by 85.23% and 95.88% respectively when full-bit-depth motion images are required. The bandwidth reduction and the ADC power reduction can be further improved to 87.50% and 98.48% respectively if only binary motion images are needed.

An improved recycling folded cascode operational transconductance amplifier with gain boosting and enhanced phase-margin is proposed. Among four variants of folded cascode amplifiers that have been implemented in TSMC 0.18μm CMOS process under same power and area constraints, the proposed amplifier achieves the lowest settling error of less than 0.5% compared to 1.1% settling error by Improved Recycling Folded Cascode (IRFC), 1.4% settling error by Recycling Folded Cascode (RFC) and 30% settling error by conventional Folded Cascode (FC) amplifier. This performance enhancement is attributed to 30dB increment in low-frequency gain and 7° improvement in the phase margin when compared with the second best performing Improved Recycling Folded Cascode amplifier.

Wireless sensor network applications typically include various sensors (temperature, humidity, gas, etc.) and each sensor has different requirements of speed, noise, offset, and power consumption. In order to optimize the performance and allow long-time operation, reconfigurability is mostly desirable in the readout circuitry. In this paper, a reconfigurable time-domain comparator (RTDC) with low noise and low offset is proposed, mainly for reconfigurable SAR ADCs in wireless sensor nodes. With a supply voltage of 1.8 V, it can be dynamically reconfigured to operate in seven different modes for different sensing scenarios. From Mode 1 to Mode 7, the maximum operating speed of the comparator ranges from 182 MHz to 20 MHz with its input referred noise been reduced exponentially from 142 μV to 63.4 μV and its offset been reduced exponentially from 7.64 mV to 2.55 mV, respectively. The simulated energy efficiency is 1.27 pJ/conv in Mode 1 and it linearly increases to 9.48 pJ/conv in Mode 7. This wide operating range enables the best possible trade-off for the sensing node application at hand.

Robustness in image recognition refers to the ability to perceive an image pattern regardless of factors including camera views and locations. This paper proposes an image normalization algorithm that allows an image with arbitrary projective distortions to be recognized efficiently. The normalization algorithm calculates the required projective transformation matrix using image moments. For an input image, a set of 8 output images that are independent of projective deformations are generated. The proposed algorithm is evaluated on three benchmark data sets. The experimental results show that the proposed normalization is significantly more accurate than the existing rank minimization and affine normalization methods.

Gas classification with an array of sensors is challenging for real life applications due to the limited amount of available training data of gases. Different pattern recognition algorithms are successfully used for gases identification, but their performance is degraded when the training and testing of these algorithms is done with different concentrations data. In this paper, we are using a binary decision tree approach for gas classification, and we are considering difference in the sensitivities of the sensors in every pair of a multi-sensor array as an input attribute for the tree. Suitable pairs of sensors are found by exploring their capability to split the available gases data samples at the decision node of the tree into two branches. A distance metric is used to select a single sensor pair in the case of more than one pair of sensors for the gases distribution at the decision node. The selected pairs of sensors learned during the training phase at the decision nodes are applied on the test data vectors. The effectiveness of our algorithm is successfully verified on the acquired data set with an array of seven metal oxide gas sensors for five different gases.

This paper describes a SAR ADC interface circuit, where the input sensing voltage from a bipolar high voltage domain is linearly translated into the low voltage domain where the SAR ADC operates. The proposed interface circuit employs the principle of charge transfer amplifier to deliver information between two different power domains, in one step, without static power consumption, even if both domains do not share the the same ground voltages. To implement the charge transfer scheme using standard asymmetric LDMOS, we propose a novel dynamic body biased high voltage transmission gate. Prototype simulation using a standard 24V BCDMOS process shows that the proposed circuit draws 2.12μW of power when it senses a voltage that swings between +10V and -10V at 1 kSPS sampling frequency.

A very low power optical wireless receiver for use in low rate, short range applications, in general, and for use in retinal prosthesis application, in particular, is proposed. Conventional optical wireless receivers are based on transimpedance amplifier and consume large static power which is not suitable for low power biomedical applications. The proposed design consumes no static power. Robust background current rejection is achieved through the use of modulation in polarization domain. A low power receiver has been designed and simulated in 0.18 μm CMOS technology. It consumes 396 nW with a 1.8V supply at a data rate of 32 Kbit/s with a Figure-of-Merit (FoM) of 12pJ/bit. DC Photocurrent of 0 to 300nA can be rejected with a sensitivity of -52 dBm. The receiver can be operated at data rate of 512 Kbps with a sensitivity of -40dbm when sampled twice per bit.

In this paper, we present a multiprecision (MP) reconfigurable multiplier that incorporates variable precision, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the user's requirements (e.g., throughput), a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency. Adapting to the run-time workload of the targeted application, razor flip-flops together with a dithering voltage unit then configure the multiplier to achieve the lowest power consumption. The single-switch dithering voltage unit and razor flip-flops help to reduce the voltage safety margins and overhead typically associated to DVS to the lowest level. The large silicon area and power overhead typically associated to reconfigurability features are removed. Finally, the proposed novel MP multiplier can further benefit from an operands scheduler that rearranges the input data, hence to determine the optimum voltage and frequency operating conditions for minimum power consumption. This low-power MP multiplier is fabricated in AMIS 0.35- μm technology. Experimental results show that the proposed MP design features a 28.2% and 15.8% reduction in circuit area and power consumption compared with conventional fixed-width multiplier. When combining this MP design with error-tolerant razor-based DVS, PP, and the proposed novel operands scheduler, 77.7%-86.3% total power reduction is achieved with a total silicon area overhead as low as 11.1%. This paper successfully demonstrates that a MP architecture can allow more aggressive frequency/supply voltage scaling for improved power efficiency.

The recent popularity of social networking websites have resulted in a greater usage of internet bandwidth for sharing multimedia content through websites such as Facebook and YouTube. Moving large volumes of multi-media data through limited network resources remains a technical challenge to this day. The current state-of-art solution in optimizing cache server utilization depends heavily on efficient caching policies to determine content priority. This paper proposes a Fast Threshold Spread Model (FTSM) to predict the future access pattern of multi-media content based on the social information of its past viewers. The prediction results are compared and evaluated against ground truth statistics of the respective YouTube video. A complexity analysis on the proposed algorithm for large datasets along with the correlation between Facebook social sharing and YouTube global hit count are explored.

This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mVrmsunder 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.

In this paper, a novel CMOS-compatible ZnO nanocomb-based gas sensor is presented. Compared with previously reported implementations, the proposed ZnO nanocombs feature multiple conducting channels and much larger effective sensing area, both of which result in dramatically improved sensitivity (6.54 for 250 ppm CO), response time (3.4 min) and recovery time (0.24 min). In addition, by operating the gas sensor at room temperature, additional power-hungry heating components inevitable in traditional implementations are completely removed. This not only leads to low power consumption, but also avoids the high-temperature-caused reliability degradation when integrated with CMOS circuitry.

A sigma delta (ΣΔ) ADC for sensing application is presented in this paper. Several techniques are adopted to implement a low power high dynamic range ADC. Firstly, a single-stage inverter replaces the commonly used differential amplifier, in order to reduce the static current. Secondly, the normal NMOS transistor in the inverter stage is replaced by a high threshold device. As a result, with the same transistor size and supply voltage, the gain of the inverter can be enhanced while the short circuit current can be reduced. Thirdly, the charge leakage due to the forward-based parasitic diode is eliminated by using a charge protection switch and rearranged reference scheme. The proposed ΣΔ ADC is implemented and fabricated using TSMC 0.18μm technology. The simulation result shows that for a 1.8V supply, 25MHz sampling frequency and 125 oversampling ratio, the power consumption is 63.7μW and 116μW, dynamic range is 80dB and 83dB, the ENOB is 11.5 and 11.7bit for a single-ended and a pseudo-differential configurations, respectively. The presented ADC scheme can be applied in a Full HD image sensor running at up to 50 frames/s.

In this paper, a smart temperature sensor working at a supply voltage as low as 0.9V over the full military temperature range is presented. Low voltage operation is achieved by biasing the front-end BJT pairs with different emitter currents for two different sensing ranges, from -55°C to 30°C and from 20°C to 125°C, respectively. A second-order inverter-based ΣΔADC with dynamic element matching (DEM) and input signal chopping to control the conversion error to within 0:2°C is used for digital readout. Front-end bias currents are selected during the design stage to minimize the induced sensing error. The proposed sensor is implemented using the TSMC 0.18μm 1P6M process. Simulation result shows that a +1°C=-0:1°C sensing error using one-point calibration can be achieved from -55°C to 125°C. At a sampling speed of 20 samples/s, the sensor consumes 3.4μA and 4.7μA in the low temperature range and the high temperature range, respectively.

Existing gas recognition techniques rely on complex signal processing techniques. This paper presents a simple bio-inspired gas recognition technique, exploiting fundamental characteristics of the organization of the olfactory pathway. The technique was validated using an-in house custom-fabricated tin gas sensor array together with three target gases: ethanol, methane, and carbon monoxide. Experimental results show that the proposed approach provides high accuracy, enabling the concept of a fully integrated electronic nose.

People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip verification errors that result from lack of clear communication between designers, and projects that are considered in their own isolated environment of technical challenges rather than the broader context of their environment or application.

In Pulse-Width Modulation (PWM) image sensors the incident light intensity is represented by the timing of pulses. Exceptionally high dynamic range (DR) and improved signal-to- noise-ratio (SNR) have been demonstrated for this class of image sensors. Unfortunately, their spatial resolution is limited by the need of an in-pixel memory to record the timing information. The AER protocol is an attractive method for removing this overhead, since pixel trigger events can be sent as address vectors, and in- pixel data memories are no longer required. Regrettably, the need to send address vectors can place an increased burden on the communication channel and will limit the array resolution, frame-rate, and image quality. In this paper, we present a low- complexity AER Block Compression (AERBC) algorithm which exploits the statistically ordered nature of AER pixel arrays. The address vector overhead can be dramatically reduced under this scheme. Only 0.0625 comparisons and 0.125 subtractions are performed for each pixel, and on average 30.82 dB PSNR can be achieved at 1.0 bit-per-pixel code rate. A general strategy is also developed here to optimize AERBC parameters so a balance between performance and hardware resources can be reached.

In this paper, we present a low cost CMOS polarimetric ophthalmoscope scheme enabling the capture of the retinal abnormalities that are unique to cerebral malaria. The proposed technology, which can be integrated into cellphones, offers the basis for quick and non-invasive screening of cerebral malaria. In addition, we report a high quality micropolarizer array for the proposed polarimetric ophthalmoscope, exploiting “guest-host” interactions in liquid crystals. With dichroic azodye-1 (AD1) molecules as the “guest” and nematic liquid crystal (NLC) molecules as the “host”, we demonstrate a better control of the molecular orientation of the “guest”, which in turn results in a ~25% increase of the major principal transmittance and a 139% increase of the peak extinction ratio. The proposed micropolarizer fabrication technology is simple and cost-effective, requiring only selective photo-patterning of a “guest-host” polymer spincoated over the image sensor.

This paper presents the architecture, algorithm, and VLSI hardware of image acquisition, storage, and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. The pixel-level memory is used to store the uncompressed illumination data during the integration mode as well as the compressed illumination data obtained after the compression stage. An adaptive quantization scheme based on fast boundary adaptation rule (FBAR) and differential pulse code modulation (DPCM) procedure followed by an online, least storage quadrant tree decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including 64×64 pixels, read-out and control circuitry as well as an on-chip compression processor was implemented in 0.35 μm CMOS technology with a silicon area of 3.2×3.0 mm2and an overall power of 17 mW. Simulation and measurements results show compression figures corresponding to 0.6-1 bit-per-pixel (BPP), while maintaining reasonable peak signal-to-noise ratio levels.

This paper proposes a novel energy harvesting technique based on an asynchronous pixel structure and an efficient energy generation scheme, referred to as avalanche energy generation (AEG). The key idea behind using an asynchronous type of pixel is to lower the power consumption by enabling only active pixels to be read-out after which they enter into a power generation mode. In this mode, the on-pixel photodetector itself will be used to harvest the light energy from the environment and make it available to active pixels. A very interesting feature about our proposed approach is that during a frame capture, critical energy is mainly required for starting-up activity. Once a group of pixels have been read-out, the available energy will rise and more array activity will contribute to the generation of more energy, hence creating an avalanche effect. In contrast to other early designs of energy harvesting image sensors, our scheme uses the photodetector itself for power generation. This results in better utilization of the photosensitive area and more importantly an improved energy generation scheme. Detailed power analysis and extensive simulation results are provided in this paper, which validate the proposed concept. Three test structures have been fabricated in AMIS 1-poly, 5-metal CMOS 0.35-m n-well process. The power generation process and event generation have been successfully verified experimentally.

In this paper, we present a 4T low-power linear output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors and four control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32 × 32 image sensor array prototype, fabricated using AMS 0.35-μm process. The pixel size is 6.5 × 6.5 μm2with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply.

The concept of compressive acquisition image sensor is to compress data while sensing and prior to storage. In this paper, the concept of compressive acquisition image sensor is developed, implemented and experimentally validated for both spatial and temporal domains. In the proposed scheme, the image sensor array is divided into quadrants integrating logic circuitry which performs online spatial compression of the raw data prior to storage. The quadrants are subsequently further classified into background/non-background quadrants by an off-array judge logic which enables to adaptively track the associated temporal information. Temporal redundancy between frames is hence removed in the readout phase. The proposed compressive acquisition algorithm is simulated and experimentally validated for both spatial and temporal domains through a hardware prototype. Experimental results show that the proposed algorithm enables more than 50% memory saving at a PSNR level of 26 dB with around 0.5 BPP. This result not only greatly reduces the memory requirements for a digital pixel CMOS image sensor, but also results in area saving as data is only stored after being compressed.

Electronic nose (EN) system based on an array of gas sensors and its recognition techniques have been widely investigated in recent decades. However, the integration of a portable EN system is not mature yet. We present an integrated EN system based on an array of gas sensor fabricated in our in-house foundry. A data acquisition technique based on a resistance-to-time conversion is proposed enabling to remove the need for an analog-to-digital converter enabling to reduce the power consumption and area. This ADC-free system is implemented in a multi-chip platform and enabling gas sensing and recognition functionalities. This system is compact, low cost and low power which is suitable for portable applications. Both sensing and recognition operations have been successfully demonstrated in our demo system.

In this paper, a compact time-domain Digital Pixel Sensor (DPS) is proposed. The Pulse Width Modulation (PWM) based sensor employs a multi-reset integration scheme enabling sequential acquisition of high resolution (8-bit) light intensity while using only a single pixel memory. The proposed multi-reset integration method reduces the memory requirements at the pixel-level, without impacting the pixel encoding resolution, as only one bit memory per pixel is required compared to the eight bits memory in conventional pixel architecture. As a consequence, both the pixel size and the fill factor are significantly improved. A near-optimal timing control unit coupled with a linearization circuit is proposed in order to limit the timing penalty incurred by the proposed integration method enabling to maintain high frame rates. A 64×64 sensor array was fabricated using AMS 0.35μm CMOS technology. A pixel size of 23μm × 21μm with a fill factor of 23% is achieved, resulting in over 75% reduction in terms of pixel size and doubling the pixel fill-factor as compared to a conventional 8-bit DPS. Simulation results demonstrate the feasibility of the proposed scheme while achieving a dynamic range higher than 100 dB as well as good linearity of the Analog to Digital Conversion (ADC) response.

This paper presents a gas identification circuit for tin oxide (SnO2) gas sensors. The proposed circuit uses 2 gas sensors with different characteristics to achieve gas identification. A spike train is generated during operation, with the frequency of spike occurrence being gas dependent but concentration invariant. As a result, the spike firing frequency can be used to achieve gas identification. The calibration of this readout technique requires only a single exposure to the target gases to extract the sensor resistances. The low complexity processing is suitable for on-chip implementation. The functionality of this circuit has been validated with real data from our in-house fabricated sensors.

In this paper, a 32×32-bit low power multi-precision multiplier is described, in which each building block can be either an independent smaller-precision multiplier or work in parallel to perform higher-precision operations. The proposed multi-precision multiplier enables voltage and frequency scaling for low power operation, while still maintaining full throughput. According to user's arbitrary throughput requirements, the highly dynamic voltage and frequency scaling circuits can autonomously configure the multiplier to operate with the lowest possible voltage and frequency to achieve the lowest power consumption. By carrying out optimizations at the algorithmic and architectural levels, we have completely removed silicon area and power overheads which is always associated with the reconfigurability features. The 32×32-bit low power multi-precision multiplier has been implemented in TSMC 0.18 μm technology. Compared with fixed-width multipliers, the proposed design features around 13.8% and 30% reduction in circuit area and power, respectively. Multi-precision processing featured in this paper accordingly enables voltage and frequency scaling resulting in up to 68% reduction in power consumption.

In this paper, we propose a liquid-crystal mi-cropolarimeter (LCMP) array with high spatial resolution for real-time linear and circular polarization imaging in visible spectrum. LCMPs for extracting 0°, 90° linearly and right-handed circularly polarized components of incident light are implemented by micro-patterning a liquid crystal (LC) layer on top of a 45° oriented ultra-thin metal-wire-grid polarizer (MWGP). A compact LCMP pitch of 5μm × 5μm is achieved with sulfonic-dye-1 (SD1) as the LC alignment material. In addition, these micron-scale LCMPs feature ~5μm overall thickness and ~1100 extinction ratio. Reported experimental results validate the concept of real-time linear and circular polarization image sensing and processing with targets illuminated by collimated artificial light.

In this paper, a new design paradigm referred to as compressive acquisition CMOS image sensors is introduced. The idea consists of compressing the data within each pixel prior to storage, and hence, reducing the size of the memory required for digital pixel sensor. The proposed compression algorithm uses a block-based differential coding scheme in which differential values are captured and quantized online. A time-domain encoding scheme is used in our CMOS image sensor in which the brightest pixel within each block fires first and is selected as the reference pixel. The differential values between subsequent pixels and the reference within each block are calculated and quantized, using a reduced number of bits as their dynamic range is compressed. The proposed scheme enables reduced error accumulation as full precision is used at the start of each block, while also enabling reduced memory requirement, and hence, enabling significant silicon area saving. A mathematical model is derived to analyze the performance of the algorithm. Experimental results on a field-programmable gate-array (FPGA) platform illustrate that the proposed algorithm enables more than 50% memory saving at a peak signal-to-noise ratio level of 30 dB with 1.5 bit per pixel.

This paper presents a robust gas identification technique for tin oxide (SnO2) gas sensors. The proposed technique generates a unique spike pattern or signature for each sensed gas, irrespective of its concentration. The proposed gas identification technique is insensitive to drift in the sensor baseline resistance. Furthermore, its calibration requires a single measurement to be made for each targeted gas. The proposed spike-based gas identification technique has been implemented in TSMC 0.18 mum CMOS technology and validated using experimental data from a fabricated in-house 4 times 4 SnO2gas sensor array. Reported results reveal a 10% increase in correct gas detection rate.

In this paper, the architecture of a digital pixel sensor (DPS) array with an online 1-bit predictive coding algorithm using Hilbert scanning scheme is proposed. The architecture of the sensor array reduces by more than half the silicon area of the DPS by sampling and storing the differential values between the pixel and its prediction, featuring compressed dynamic range and hence requiring limited precision (only 1-bit signed value in the proposed architecture as compared to 8-bit unsigned full precision). Hilbert scanning is used to read-out the pixel's value, hence avoiding discontinuity in the read-out path, which is shown to improve the quality of the reconstructed image. The Hilbert scanning path is all carried out by hardware wire connection without increasing the circuit complexity of the sensor array. Reset pixels are inserted into scanning path to overcome the error accumulation problem inherent in predictive coding. System level simulation results show a PSNR of around 25dB can be reached while using the proposed 1-bit Hilbert predictive coding algorithm. VLSI implementation results illustrate a pixel level implementation featuring a pixel size reduction of 67% with a fill-factor of 40% compared with a standard PWM DPS architecture.

In this paper, a Time Domain CMOS Temperature Sensor with Differential Temperature Sensing Circuit and Reduced Supply Sensitivity is presented. Differential temperature sensing is achieved by using two delay generators, each for generating positively and negatively proportional to temperature delays respectively. The effective temperature signal can then be increased for quantization. The variation in supply voltage is sensed and converted to bias currents proportional to supply voltage. Temperature error due to 10% supply voltage variation can be reduced to less than ±1°C. A temperature dependent pulse will be generated and then digitized by a ripple counter using an external clock signal. Simulation results show that a ±0.6°C with two-point calibration can be achieved with a temperature variation from 0°C to 100°C. The circuit consumes 12μA and 70μA in static and temperature acquiring mode, respectively, and has a sampling rate of more than 80k samples/s.

This paper presents a fast algorithm for generating Hilbert address for hardware implementation with low storage requirement. This work avoids the use of recursive functions as compared with Quinqueton's work, and eliminates complicated bit manipulations as proposed by Butz, and does not use any look-up-tables as implemented by Kamata. Each address can be obtained in one clock cycle by one-to-one mapping using a simple incremental counter and cascading of multiplexers. The merit of our method is that it achieves very high speed when computing the Hilbert address which requires little memory storage.

This paper presents a 4 times 4 logarithmic spike-timing encoding scheme used to translate the output of an integrated tin oxide gas sensor array into spike sequence, which is exploited to perform gas recognition. Hydrogen, ethanol and carbon monoxide were used to characterize the gas sensor array. The collected data were then used to test the proposed circuit for spike encoding and gas recognition. Simulation results illustrate that a particular analyte gas generates a unique spike pattern with certain spike ordering sequence, which is independent of the gas concentration. This unique spike sequence can thus be used to recognize different gases. In addition, the concentration information can also be extracted from the time-to-the-first spike in the sequence making it possible to perform not only gas/odor recognition but quantification as well.

In this paper, a Variable Reference Time Domain Encoding CMOS image sensor is presented. The time domain encoding vision sensor is known to suffer from slow conversion time, especially at low level of illumination. This is due to limited photocurrent generated to discharge the photodiode junction voltage to the reference voltage. A variable referencing scheme is proposed so that the reference voltage will be modulated and bounded by a specified deadline. The pixel consists of a photodiode, an analogue comparator, an 8-bit SRAM, a SR latch, and occupies an area of 32μm×35μm, with a fill-factor of 12.6 % using a 0.35μmCMOS process. Simulation results show that signal conversion can be achieved by using pre-defined threshold voltages. By using four levels of reference voltage and ⅒ of the original conversion time required by the original time domain encoding, over 70% reduction in total integration time can be achieved.

This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (HE). The pixel values are read-out using an asynchronous handshaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1times0.6 mm2). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in AMIS 0.35 mum process with a silicon area of 3.1times3.2 mm2. Successful operation of the prototype is illustrated through experimental measurements

In this paper we propose a second generation time-to-first-spike (TFS) pixel based on an asynchronous self power-off architecture. In this architecture time-to-first spike is used to encode the photocurrent information. Once the first spike is received and read-out using an address event representation (AER), the pixel is forced into standby mode by cutting off the power supply of itself. Simulation results shows that significant reduction in leakage power is achieved which is a major concern when implementing high resolution image sensor in deep-submicron technology. Based on this proposed architecture a prototype was designed in UMC 0.18 /spl mu/m technology. Each pixel includes a photodiode, an event generator and hand-shaking communication protocol using 15 transistors. Each pixel occupies an area of 8.3 /spl times/ 8.3/spl mu/m/sup 2/ with a fill factor of 15%. In addition, the new generation TFS sensor features reduced depth of the arbitration tree using high-radix AER building block resulting in reduced overall delay.

A CMOS digital pixel sensor (DPS) with programmable resolution and reconfigurable conversion time is described. The chip features a unique architecture based on the pulse width modulation (PWM) technique and operates with either an 8-b or 4-b accuracy. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a shorter conversion time and a two times increase in spatial resolution. Two quantization schemes are studied, namely, the uniform and the nonuniform time-domain quantizers, which are referred to as UQ and NUQ, respectively. It is shown that the latter scheme not only permits to linearize the nonlinear response of the PWM sensor, but also allows to significantly speed up the conversion time, particularly for wide dynamic range and low coding resolutions. A prototype of 32/spl times/32/64/spl times/32 pixels has been fabricated using 1-poly, 5-metal CMOS 0.35-/spl mu/m n-well standard process. Power dissipation is 10 mW at V/sub DD/=3.3 V, dynamic range is 90 dB, while dark current was measured at 1 pA. The reconfiguration features of the chip have been verified experimentally.

Gaussian mixture models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications, but using such classifiers can require large storage and complex processing units due to exponential calculations and a large number of coefficients involved. This poses a serious problem for portable real-time pattern recognition applications. In this paper, first the performance of GMM and its hardware complexity are analyzed and compared with a number of benchmark algorithms. Next, an efficient digital hardware implementation is proposed. A number of design strategies are proposed in order to achieve the best possible tradeoffs between circuit complexity and real-time processing. First, a serial-parallel vector-matrix multiplier combined with an efficient pipelining technique is used. A novel exponential calculation circuit based on a linear piecewise approximation is proposed to reduce hardware complexity. The precision requirement of the GMM parameters in our classifier are also studied for various classification problems. The proposed hardware implementation features programmability and flexibility offering the possibility to use the proposed architecture for different applications with different topologies and precision requirements. To validate the proposed approach, a prototype was implemented in 0.25-mum CMOS technology and its operation was successfully tested for gas identification application

The pattern recognition problem for real life applications of gas identification is particularly challenging due to the small amount of data available and the temporal variability of the instrument mainly caused by drift. We present a gas identification approach based on class-conditional density estimation using Gaussian mixture models (GMM). A drift counteraction approach based on extracting robust features using a simulated drift is proposed. The performance of the retrained GMM shows the effectiveness of the new approach in improving the classification performance in the presence of artificial drift.

This paper describes a hardware implementation of threshold network ensembles (TNE) for classification applications. We first describe the algorithm and compare its performance with those of individual classifiers such as binary neural network and support vector machine (SVM). The effect of limited precision on the performance of threshold network ensembles is also investigated. The proposed multi-precision architecture is then mapped into a scalable systolic architecture implemented first on a single VLSI chip. The modularity and the easy programability of the basic chip has made possible the extension of the architecture to a low cost multi-chip solution. We propose a 3D packaged circuit in which 12 basic chips have been integrated into a very compact volume of (2 /spl times/ 2 /spl times/ 0.7)cm/sup 3/. Successful operation of the 3D prototype is demonstrated through experimental test results of the chip.

A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.

In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 /spl mu/m CMOS technology.