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Thomas M. McWilliams

dblp:85/183 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 83% Integrated circuit design · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification		 0.011980
Verification of timing constraints on large digital systems · DAC 1980
Electronic design automation › hardware verification and test › timing verification
timing constraint verification		 0.011980
Verification of timing constraints on large digital systems · DAC 1980
Electronic design automation › hardware verification and test
timing verification		 0.011980
Verification of timing constraints on large digital systems · DAC 1980
Integrated circuit design › digital circuit design
logic design		 0.011978
SCALD: Structured Computer-Aided Logic Design · DAC 1978
Electronic design automation
physical design		 0.011978
The SCALD physical design subsystem · DAC 1978
YearPublicationVenuePosition
1985 Easing the Transition from Design to Test
Thomas M. McWilliams
 ITC1
1980 Verification of timing constraints on large digital systems
abstract
A new approach to the verification of the timing constraints on large digital systems has been developed. The associated algorithm is computationally very efficient, and provides early and continuous feedback about the timing aspects of synchronous sequential circuits as they are designed. It also provides means for conveniently verifying the design in sections, permitting the section-by-section timing verification of designs which are too large to examine as a unit on existing computer systems. A system using this algorithm has been implemented, and has been used to verify the timing constraints on the design of the S-1 Mark IIA processor.
Thomas M. McWilliams
 DAC1
1978 SCALD: Structured Computer-Aided Logic Design
Thomas M. McWilliams, Lawrence C. Widdoes Jr.
 DAC1
1978 The SCALD physical design subsystem
Thomas M. McWilliams, Lawrence C. Widdoes Jr.
 DAC1