AMULET2e is an embedded system chip incorporating a 32-bit ARM-compatible asynchronous processor core, a 4-Kb pipelined cache, a flexible memory interface with dynamic bus sizing, and assorted programmable control functions. Many on-chip performance-enhancing and power-saving features are switchable, enabling detailed experimental analysis of their effectiveness. AMULET2e silicon demonstrates competitive performance and power efficiency, ease of system design, and it includes innovative features that exploit its asynchronous operation to advantage in applications that require low standby power and/or freedom from the electromagnetic interference generated by system clocks.

An asynchronous implementation of the ARM microprocessor has been developed using an approach based on Sutherland's Micropipelines. The design allows considerable internal asynchronous concurrency. This paper presents the rationale for the work, the organization of the chip, and the characteristics of the prototype silicon. The design displays unusual properties such as nondeterministic (but bounded) prefetch depth beyond a branch instruction, a data dependent throughput, and employs a novel register locking mechanism. This work demonstrates the feasibility of building complex asynchronous systems and gives an indication of the costs and benefits of the Micropipeline approach.

Standard micropipelines use simple two-phase control circuits. The latches employed on AMULET1 are level sensitive, so two- to four-phase converters are required in each latch controller. To avoid this overhead an investigation has been carried out into four-phase micropipeline control circuits; this has thrown up several design issues relating to cost, performance and safety, and forms a useful illustration of asynchronous design techniques.

An asynchronous implementation of the ARM microprocessor has been designed and fabricated based on Sutherland's Micropipeline approach. Reviews of this work have shown that considerable performance improvement may be possible in a number of key design areas. This paper assesses the effects of different design styles on the micropipeline latch structures used. The original design has latch structures based on pass-transistor transparent latches. An evaluation of the use of single-phase transparent latch structures is given plus the application of 2-phase and 4-phase control techniques.>

AMULET1 is a fully asynchronous implementation of the ARM microprocessor which was designed at Manchester University between 1991 and 1993. First silicon arrived in April 1994 and was found to be functional, demonstrating that asynchronous design of complex circuits is feasible with present day CAD tools. This paper presents the motivation for the work, some of the design choices which were made, the problems which were encountered during the development of the design and the characteristics of the device itself. The future potential for asynchronous circuits is also discussed.>

A high-performance register bank is a central component of a RISC processor. A novel register bank design has been developed, as an integral part of a self-timed implementation of a commercial RISC microprocessor, to address the problem of register interlocking in an asynchronous micropipelined execution unit. The problem in an asynchronous design is to maintain coherent register operation while allowing concurrent read and write accesses with arbitrary timing. The solution presented here includes a novel arbiter-free locking mechanism which enables efficient read operations in the presence of multiple pending write operations.>

“ARGOS” (ARGonne Operating System), which runs on a Xerox Sigma 5 hardware configuration, provides a dynamic multiprogrammed environment which supports the following: data acquisition and interactive control for numerous (currently 19) independently running on-line laboratory experiments; three interactive graphics terminals; FORTRAN IV-H executing at each of 23 remote time-shared terminals; a jobstream from open-shop batch processing; long-term low priority computations (100 CPU hours). The system guarantees the protection of each user's interests by the utilization of the hardware memory-protection feature, internal clocks and disallowing the execution of privileged instructions by user programs. The system is interrupt-driven, with each task running to completion, contingent on its priority. System resources are provided on a first come first served basis, except that rotating memory is queued by request position. System CALLs provide users full access to hardware capability, thus providing user-directed file formats and insuring a minimum of system overhead. However, at some sacrifice in overhead, the user can make use of FORTRAN record-blocking. Core memory, disk space and magnetic tape usage, are assigned dynamically. Parametrization of the system is such that terminal characteristics are specified (one parameter card/terminal) at boot-in time (once/week after preventive maintenance).