Demo Data from VLDB 2026 / reviewers in the wild / expert
Matthias A. Blumrich
dblp:85/2383
· DBLP profile ↗
10ranked-venue papers
4as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 10 · 4 first-authorSoftware engineering, systems software and programming languages · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
8 papers |
Interconnection networks and networks-on-chip · 44% High-performance computing · 20% Storage systems · 9% | |
| Interdisciplinary, comprehensive, and emerging computing
1 paper |
Computational science and engineering · 100% |
Topics — the 20 heaviest of 25, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › switch architecture
high-radix switch |
0.3 | 1 | 2018 | Exploiting idle resources in a high-radix switch for supplemental storage · SC 2018 |
Memory systems
cache coherence |
0.1 | 1 | 2008 | Design and implementation of the blue gene/P snoop filter · HPCA 2008 |
High-performance computing › large-scale simulation
quantum chromodynamics simulation |
0.1 | 1 | 2006 | Gordon Bell finalists II - The BlueGene/L supercomputer and quantum ChromoDynamics · SC 2006 |
High-performance computing › supercomputing
supercomputer performance |
0.1 | 1 | 2006 | Gordon Bell finalists II - The BlueGene/L supercomputer and quantum ChromoDynamics · SC 2006 |
Interconnection networks and networks-on-chip
network interface |
0.0 | 3 | 1998 | Design Choices in the SHRIMP System: An Empirical Study · ISCA 1998 Protected, User-Level DMA for the SHRIMP Network Interface · HPCA 1996 Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer · ISCA 1994 |
High-performance computing › supercomputing
bluegene/l |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
High-performance computing
supercomputing |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
Integrated circuit design
system-on-chip |
0.0 | 1 | 2002 | An overview of the BlueGene/L Supercomputer · SC 2002 |
Processor architecture and microarchitecture
chip multiprocessor |
0.0 | 1 | 2008 | Design and implementation of the blue gene/P snoop filter · HPCA 2008 |
High-performance computing
cluster computing |
0.0 | 1 | 1998 | Design Choices in the SHRIMP System: An Empirical Study · ISCA 1998 |
Operating systems › i/o
i/o subsystem |
0.0 | 1 | 1996 | Protected, User-Level DMA for the SHRIMP Network Interface · HPCA 1996 |
Parallel and multicore computing › parallel libraries
communication library |
0.0 | 1 | 1996 | Early Experience with Message-Passing on the SHRIMP Multicomputer · ISCA 1996 |
Distributed systems › operating system support › interprocess communication
message-passing communication |
0.0 | 1 | 1996 | Early Experience with Message-Passing on the SHRIMP Multicomputer · ISCA 1996 |
Parallel and multicore computing
parallel programming runtimes |
0.0 | 1 | 1996 | Early Experience with Message-Passing on the SHRIMP Multicomputer · ISCA 1996 |
Interconnection networks and networks-on-chip › network interface
memory-mapped network interface |
0.0 | 1 | 1994 | Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer · ISCA 1994 |
Parallel and multicore computing › parallel programming models
message passing |
0.0 | 1 | 1994 | Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer · ISCA 1994 |
Memory systems › memory management › virtual memory
address translation |
0.0 | 1 | 1996 | Protected, User-Level DMA for the SHRIMP Network Interface · HPCA 1996 |
Parallel and multicore computing
multicomputer |
0.0 | 1 | 1996 | Early Experience with Message-Passing on the SHRIMP Multicomputer · ISCA 1996 |
Memory systems › virtual memory management
memory mapping |
0.0 | 1 | 1994 | Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer · ISCA 1994 |
Memory systems › memory management
virtual memory |
0.0 | 1 | 1994 | Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer · ISCA 1994 |
Methods — techniques the papers use, named apart from their topics
scaling analysis · 0.1simulation · 0.1system architecture design · 0.0performance scaling studies · 0.0kernel support · 0.0hardware-software co-design · 0.0empirical study · 0.0design space exploration · 0.0zero-copy protocol · 0.0performance evaluation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Exploiting idle resources in a high-radix switch for supplemental storage
Matthias A. Blumrich, Nan Jiang 0009, Larry Dennison |
SC | 1 |
| 2008 | Design and implementation of the blue gene/P snoop filterabstractAs multi-core processors evolve, coherence traffic between cores is becoming problematic, both in terms of performance and power. The negative effects of coherence (snoop) traffic can be significantly mitigated through snoop filtering. Shielding each cache with a device that can squash snoop requests for addresses known not to be in cache improves performance significantly for caches that cannot perform normal load and snoop lookups simultaneously. In addition, reducing snoop lookups yields power savings. This paper describes the design of the Blue Gene/P snoop filters, and presents hardware measurements to demonstrate their effectiveness. The Blue Gene/P snoop filters combine stream registers and snoop caches to capture both the locality of snoop addresses and their streaming behavior. Simulations of SPLASH-2 benchmarks illustrate tradeoffs and strengths of these two techniques. Their combination is shown to be most effective, eliminating 94-99% of all snoop requests using very few stream registers and snoop cache lines. This translates into an average performance improvement of almost 20% for the NAS benchmarks running on an actual Blue Gene/P system. Valentina Salapura, Matthias A. Blumrich, Alan Gara |
HPCA | 2 |
| 2006 | Gordon Bell finalists II - The BlueGene/L supercomputer and quantum ChromoDynamicsabstractWe describe our methods for performing quantum chromodynamics (QCD) simulations that sustain up to 20% of the peak performance on BlueGene supercomputers. We present our methods, scaling properties, and first cutting edge results relevant to QCD. We show how this enables unprecedented computational scale that brings lattice QCD to the next generation of calculations. We present our QCD simulation that achieved 12.2 Teraflops sustained performance with perfect speedup to 32K CPU cores. Among other things, these calculations are critical for cosmology, for the heavy ion experiments at RHIC-BNL, and for the upcoming experiments at CERN-Geneva. Furthermore, we demonstrate how QCD dramatically exposes memory and network latencies inherent in any computer system and propose that QCD should be used as a new, powerful HPC benchmark. Our sustained performance demonstrates the excellent properties of the BlueGene/L system. Pavlos Vranas, Gyan Bhanot, Matthias A. Blumrich, Dong Chen 0005, Alan Gara, Philip Heidelberger, Valentina Salapura, James C. Sexton |
SC | 3 |
| 2002 | Blue Gene/L, a System-On-A-ChipabstractSummary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh |
CLUSTER | 6 |
| 2002 | An overview of the BlueGene/L SupercomputerabstractThis paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates |
SC | 10 |
| 1999 | Shared virtual memory with automatic update supportabstractShared virtual memory systems provide the abstraction of a shared address space on top of a messagepassing communication architecture. The overall performance of an SVM system therefore depends on both the raw performance of the underlying communication mechanism and the e#ciency with which the SVM protocol uses that mechanism. The Automatic Update Release Consistency (AURC) protocol was proposed to take advantage of simple memory-mapped communication and automatic update support to accelerate a shared virtual memory protocol. However, there has not yet been a real system on which an implementation of this protocol could be evaluated. This paper reports our evaluation of AURC on the SHRIMP multicomputer, the only hardware platform that supports an automatic update mechanism. Automatic update propagates local memory writes to remote memory locations automatically. We compare the AURC protocol with its all-software counterpart protocol, Home-based Lazy Release Consistency (HLRC). By int... Liviu Iftode, Matthias A. Blumrich, Cezary Dubnicki, David Oppenheimer, Jaswinder Pal Singh, Kai Li 0001 |
International Conference on Supercomputing | 2 |
| 1998 | Design Choices in the SHRIMP System: An Empirical StudyabstractThe SHRIMP cluster-computing system has progressed to a point of relative maturity; a variety of applications are running on a 16-node system. We have enough experience to understand what we did right and wrong in designing and building the system. In this paper we discuss some of the lessons we learned about computer architecture, and about the challenges involved in building a significant working system in an academic research environment. We evaluate significant design choices by modifying the network interface firmware and the system software in order to empirically compare our design to other approaches. Matthias A. Blumrich, Richard Alpert, Yuqun Chen, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Edward W. Felten, Liviu Iftode, Kai Li 0001, Margaret Martonosi, Robert A. Shillner |
ISCA | 1 |
| 1996 | Protected, User-Level DMA for the SHRIMP Network InterfaceabstractTraditional DMA requires the operating system to perform many tasks to initiate a transfer, with overhead on the order of hundreds or thousands of CPU instructions. This paper describes a mechanism, called User-level Direct Memory Access (UDMA), for initiating DMA transfers of input/output data, with full protection, at a cost of only two user-level memory references. The UDMA mechanism uses existing virtual memory translation hardware to perform permission checking and address translation without kernel involvement. The implementation of the UDMA mechanism is simple, requiring a small extension to the traditional DMA controller and minimal operating system kernel support. The mechanism can be used with a wide variety of I/O devices including network interfaces, data storage devices such as disks and tape drives, and memory-mapped devices such as graphics frame-buffers. As an illustration, we describe how we used UDMA in building network interface hardware for the SHRIMP multicomputer. Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li 0001 |
HPCA | 1 |
| 1996 | Early Experience with Message-Passing on the SHRIMP MulticomputerabstractThe SHRIMP multicomputer provides virtual memory-mapped communication (VMMC), which supports protected, user-level message passing, allows user programs to perform their own buffer management, and separates data transfers from control transfers so that a data transfer can be done without the intervention of the receiving node CPU. An important question is whether such a mechanism can indeed deliver all of the available hardware performance to applications which use conventional message-passing libraries. This paper reports our early experience with message-passing on a small, working SHRIMP multicomputer. We have implemented several user-level communication libraries on top of the VMMC mechanism, including the NX message-passing interface, Sun RPC, stream sockets, and specialized RPC. The first three are fully compatible with existing systems. Our experience shows that the VMMC mechanism supports these message-passing interfaces well. When zero-copy protocols are allowed by the semanti... Edward W. Felten, Richard Alpert, Angelos Bilas, Matthias A. Blumrich, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Liviu Iftode, Kai Li 0001 |
ISCA | 4 |
| 1994 | Virtual Memory Mapped Network Interface for the SHRIMP MulticomputerabstractThe network interfaces of existing multicomputers require a significant amount of software overhead to provide protection and to implement message passing protocols. The authors describe the design of a low-latency, high-bandwidth, virtual memory-mapped network interface for the SHRIMP multicomputer project at Princeton University. Without sacrificing protection, the network interface achieves low latency by using virtual memory mapping and write-latency hiding techniques, and obtains high bandwidth by providing a user-level block data transfer mechanism. The authors have implemented several message passing primitives in an experimental environment, demonstrating that their approach can reduce the message passing overhead to a few user-level instructions.> Matthias A. Blumrich, Kai Li 0001, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg |
ISCA | 1 |