This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -- 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

Test compression has become a requirement for many designs to meet the required test quality levels in reasonable test times and with acceptable test cost. This session will cover some of the tradeoffs and options available from the broad spectrum of test compression solutions. The first talk will address the difficulty when testing large numbers of logic blocks and processor cores of maintaining high test quality without a requisite increase in test cost stemming from the need to allocate substantially more pins for digital test. Simply adding more chip-level pins for testing conflicts with packaging constraints and can potentially undermine other cost-saving techniques that rely on utilizing fewer pins such as multi-site testing. What is needed instead is a DFT strategy optimized for complex SOC designs that use multicore processors-a strategy in which the architecture and automation elements work in tandem to lower test cost without compromising test quality or significantly increasing automatic test pattern generation (ATPG) runtime. This presentation highlights an optimized DFT architecture, referred to as “shared I/O” of DFTMAX, a synthesis-based test solution that has been used successfully in multicore processor designs as well as complex SOC designs. Using this approach, they were able to reduce scan test pins significantly with similar or even less ATPG patterns, without compromising test coverage, and achieve over 2X reduction in wafer level scan test time. The second talk will present many DFT techniques to reduce test time and improve coverage in the context of core wrapping. Some of these methods include using external scan chains with separate compression logic inside each place-and-route block instead of having ‘chip-top’ scan compression logic for all external scan chains from different place-and-route. In addition, some tradeoffs of using dynamic launch-on-shift/launch-on-capture (LOS/LOC) instead of static will be covered. Some other methods will be covered for preventing decompressor logic from feeding X'es during launch-on-shift test patterns and the benefits of control test-points to reduce ATPG vector counts. The final presentation will cover various methodologies for reducing the test data volume on different chips. Some work to achieve a higher compression ratio in the future will also be discussed. As with any good engineering solution, there are some constraints and tradeoffs that also need to be considered with those choices.

About half of the logic circuit transistors of a modern integrated circuit design reside inside the scan flip-flops. Even though prior work analyzed detection of defects in traditional master-slave flip-flop circuits, to the best of our knowledge, this work is the first one regarding detection of defects in a sense-amplifier-based flip-flop, which is a preferred design style in some high-speed low-power designs. In this work, we uncover a class of resistive open and resistive short defects in such a flip-flop design, which show a great difference in their detection response to launch-off-shift versus launch-off-capture due to their sensitivity to clock-gating and data input transitions.

Creating functional tests that work on an ATE has always been a significant challenge [I]. This paper identifies the fundamental mechanisms for functional test failures of an SOC on an ATE. Taking these mechanisms into account during the design process of a chip can substantially reduce the efforts needed to make functional tests work. We call this process design for functional testability (DFFT).

Rapid growth in the internet and enterprise network traffic, need by both subscribers and operators to provide for differentiated services, and the constant evolution of wireline and wireless networking functions, algorithms and standards, is leading to a high demand for ultra high speed, yet programmable, network processors and ASICs. This session will introduce the design of network processors, and highlight important validation and test challenges associated with network processors and ASICs. The first speaker in this session will review the architecture of a typical OC-192 network processor – a highly complex system-on-chip, consisting of multiple processors, specialized hardware blocks, multiple high-speed embedded memory units, and a highly concurrent and complex on-chip interconnect structure. The talk will analyze the validation and manufacturing test problems of hardware-software GHz network processor chips, which have to use aggressive architecture designs and nano-meter technologies to obtain the required multi-GHz speed, while relying on the presence of multiple processors to provide the necessary flexibility. The second talk will address testing of embedded GHz network processors. In particular, it will describe the challenges faced in testing a specific high-speed low-power network processor chip, which includes two custom-design 64-bit MIPS processors, 0.5MB of L2 cache, and multiple high speed communication blocks, such as gigabit-ethernet, hypertransport, and double-data-rate memory controllers. Some test solutions will be presented, and major test challenges that need to be addressed will be listed. The third talk in this session will address the problem of delay testing in communications chips. In communication devices such as network switches and routers, there usually are multiple unrelated clocks controlling various interfaces and logic. These multiple clock domains presents unique challenges in production testing since it becomes very difficult to predict when the expected output will show up at the pin boundary. The talk will show why delay defects need to be addressed, and how to deal with cycle uncertainty problem during production testing. It will present a novel compaction technique used to deal with the test data volume explosion resulting from including of delay defect screening tests. Proceedings of the 20 th IEEE VLSI Test Symposium (VTS’02) 1093-0167/02 $17.00 © 2002 IEEE

In most of the delay fault testing literature there is a widespread belief that a non-robust test for a path delay fault can be invalidated only through the existence of another path delay fault. In this paper the author presents an analysis of conditions that can invalidate a non-robust test, and gives four different invalidation mechanisms. Three of these mechanisms, in addition to pulse dampening, do not require the existence of another path delay fault in a circuit. He also defines pseudo-VNR tests, and shows that this is the most common interpretation of validatable-non-robust tests in the literature. Uncovering the invalidation mechanisms for non-robust tests is quite important given the fact that a large number of paths in a circuit usually do not have any robust tests.

This paper describes a highly accurate and efficient fault simulator for interconnect opens in combinational or full-scan digital CMOS circuits. The analog behavior of the wires with interconnect opens is modeled very efficiently in the vicinity of the defect in order to predict what logic levels the fanout gates will interpret and whether a sufficient IDDQ current will be flowing inside the fanout gates. The fault simulation method is based on characterizing the standard cell library with SPICE, using transistor charge equations for the site of the open, using logic simulation for the rest of the circuit, taking four different factors that can affect the voltage of an open into account, and considering the potential oscillation and sequential behavior of interconnect opens. The tool can simulate test vectors for both voltage and current measurements. Simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets are presented.

Shorts and opens are the most common types of catastrophic defects in today's CMOS ICs. In this paper, we show that an open in the interconnect wiring of a digital CMOS circuit, which permanently disconnects inputs of logic gates from their driver, can cause oscillation or sequential behavior. We present supporting experimental data collected by creating an interconnect open in a manufactured chip. We also show that the conditions for oscillation and sequential behavior are likely to occur in many interconnect opens.

We describe a highly accurate but efficient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can affect the voltage of an open, into account; and considering the oscillation and sequential behaviour potential of opens. A novel test technique based on controlling the die surface voltage is also described. We present simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets.

Shorts and opens are the most common types of defects in today's CMOS ICs. In this paper we show for the first time that an open in the interconnect wiring of a digital CMOS circuit can cause oscillation or sequential behavior. We also analyze and compare the factors affecting the probabilities for an interconnect open and a feedback bridging fault to oscillate or display sequential behavior.

We present the experimental evidence, for the first time, that the die surface can act as an RC interconnect, becoming an important factor in determining the voltage of a floating wire created by a CMOS open. We present a circuit model for this effect verified with HSPICE simulations. A detailed analysis of potential mechanisms behind this phenomenon is provided. We also present our measurement results for the trapped charge deposited on floating gates during fabrication.

We define a network break as a break fault in the p-network or in the n-network of a CMOS cell that breaks one or more transistor paths between the cell output and V/sub dd/ or GND. Previous work, mostly in the context of transistor stuck-open faults, studied test invalidation due to transient paths to V/sub dd/ or GND, and due to charge sharing. In this paper we show the importance of Miller feedthrough and feedback capacitances in network break test invalidation, which was ignored by previous work. We present a new fault simulation algorithm for network breaks, with the following novelties: First, the electrical charge coming from Miller and p-n junction capacitances is computed using a transistor charge model; this automatically handles the nonlinear nature of transistor capacitances accurately, as opposed to assuming constant capacitance values as was done in previous work. Next, we use only six voltage levels for charge computations, which allows us to create look-up tables that dramatically reduce the computation time. Finally, the maximum voltage an internal node in an n-network can acquire is about three-fourths of the V/sub dd/ voltage (instead of V/sub dd/ as assumed by previous work), and similarly, a p-network node cannot discharge all the way down to the GND voltage. Using our simulator to analyze test sets for the ISCAS'85 circuits, we found that the charge coming from Miller capacitances has a larger share in test invalidation than the charge from p-n junction capacitances. Our simulator spends less time for charge computations than it spends for transient path identification.

We present a new fault simulation algorithm for realistic break faults in the p-networks and n-networks of static CMOS cells. We show that Miller effects can invalidate a test just as charge sharing can, and we present a new charge-based approach that efficiently and accurately predicts the worst case effects of Miller capacitances and charge sharing together. Results on running our fault simulator on ISCAS85 benchmark circuits are provided. 1 INTRODUCTION Defects that occur during the IC manufacturing process can be categorized into three classes according to Hawkins et al. [7]. These classes are bridge, open circuit, and parametric defects. Open circuit defects cause breaks in the conducting materials in the layout, and contacts are particularly susceptible to such breaks. Breaks can be divided into two categories: those that physically disconnect one or more transistor gates from their drivers, and those that disconnect transistors from each other in the p-network or n-network of ...

Fastpath generates non-robust, robust or single-path-sensitization hazard-free robust path-delay tests for standard scan designs including high-impedance elements and functionally-described blocks. Results show effective and memory-efficient operation.

Presents a sequential test generation method based on Boolean satisfiability. The method produces near-minimal test sizes. The authors discuss the flexibility provided by Boolean satisfiability to extend the fault model to realistic faults. Experimental results using ISCAS-89 benchmark circuits and comparisons with previously published results are presented.>

A new method for high level synthesis is reported whose basic feature is the tight interaction and coupling of the scheduling and allocation phases providing a global direction to synthesis. A linear program based allocation is proposed which uses multifunction ALU cost estimation, and iteratively drives a tree search for scheduling. A major contribution of this paper is a new interconnect optimization algorithm which is based on several interconnect transformations for multiplexer input collapsing and merging. Several other important synthesis aspects are included, e.g. register and interconnect bindings, operation chaining and operation multicycling. The method has been implemented in C on a Sun 3/60,