Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Jaw-Wei Chi

dblp:85/3370 · DBLP profile ↗
← Back
2ranked-venue papers
1as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 70% Embedded and real-time systems · 23% Memory systems · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › leakage power reduction
cache leakage reduction
0.112011
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems · IEEE Trans. Computers 2011
Embedded and real-time systems › real-time embedded systems
hard real-time systems
0.112011
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems · IEEE Trans. Computers 2011
Energy-efficient computing
leakage power reduction
0.112011
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems · IEEE Trans. Computers 2011
Energy-efficient computing
power management
0.112011
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems · IEEE Trans. Computers 2011
Memory systems
cache management
0.012011
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems · IEEE Trans. Computers 2011

Methods — techniques the papers use, named apart from their topics

timing-aware cache leakage control · 0.1slack exploitation · 0.1
YearPublicationVenuePosition
2011 TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems
abstract
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Existing leakage reduction techniques for hard real-time systems utilize slack to turn off a CPU completely. However, turning on/off a processor involves high performance and energy overheads. Hence, a hard real-time system is very likely to have unutilized slack if only the CPU shutdown technique is used to reduce leakage. Architectural-level shutdown techniques in all instances have a much lower overheads than turning off a CPU; therefore, they can be utilized in a hard real-time system to further reduce CPU leakage. However, existing architecture-level shutdown techniques cause unpredictable performance degradation thereby unsuitable for a hard real-time system that must meet the timing constraint in all cases. This paper is the first attempt to bridge this gap. This paper focuses on cache leakage reduction and proposes the first Timing-Aware Cache Leakage Control (TACLC) mechanism. TACLC exploits system slack to turn cache lines into low-leakage states provided that the timing constraint is met. The experimental results demonstrate that TACLC effectively utilizes system slack to reduce cache leakage. For systems with low CPU utilization, TACLC achieves comparable leakage reduction to the leakage control policy that aggressively turns cache lines into low-leakage modes while neglecting the timing constraint.
Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen
IEEE Trans. Computers3
2007 Cache leakage control mechanism for hard real-time systems
abstract
Leakage energy consumption is an increasingly important issue as the technology continues to shrink. Since on-chip caches constitute a major portion of the processor’s transistor budget, several leakage control policies have been proposed to reduce cache leakage. However, these policies introduce performance unpredictability thereby not suitable for hard real-time applications that require the timing constraint is met in all cases. In this paper, we propose the first approach to apply existing low leakage circuit techniques on hard real-time applications. The proposed timing-aware cache leakage control mechanism exploits task slack time to turn cache lines into the low-leakage state provided that the timing constraint is met. The experimental results show that the proposed cache leakage control policy achieves comparable leakage reduction to the leakage control policy that aggressively turns cache lines into low-leakage modes without considering the timing constraint.
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen
CASES1