This paper presents a power-aware scheduling algorithm based on efficient distribution of the computing workload to the resources on heterogeneous CPU-GPU architectures. The scheduler manages the resources of several computing nodes with a view to reducing the peak power. The algorithm can be used in concert with adjustable power state software services in order to further reduce the computing cost during high demand periods. Although our study relies on GPU workloads, the approach can be extended to other heterogeneous computer architectures. The algorithm has been implemented in a real CPU-GPU heterogeneous system. Experiments prove that the approach presented reduces peak power by 10 percent compared to a system without any power-aware policy and by up to 24 percent with respect to the worst case scenario with an execution time increase in the range of 2 percent. This leads to a reduction in the system and service costs.

The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this performance/costs challenge is given by customizable multiprocessor system-on-chips. The approach proposed in this paper leads to the customization of multi/many processor system-on-chip at two levels of abstraction: 1) customization through application-specific hardware accelerators implemented on configurable datapath that can target three kinds of structured application-specific integrated circuit technologies: metal, via, and runtime programmable and 2) customization of the architectural parameters of the platform. The proposed platform is equipped with a design framework that assists the user in the high-level design-space exploration of signal processing applications described using the Open Computing Language (OpenCL) language. A peculiar added value of the flow is to support the migration of OpenCL kernels and tasks into pipelined hardware accelerators described using a C-level language. The platform is able to provide an average performance of 90 GOPS on a set of reference signal processing applications, and an average computational energy efficiency of 130 GOPS/W in its metal-programmable configuration. This result shows the benefits in terms of energy efficiency of hardware customization applied to multiprocessor systems with respect to many core devices such as general-purpose graphic processing units, able to provide on average 2.5 GOPS/W for the applications under analysis.

This paper describes the application space exploration of a heterogeneous digital signal processor with dynamic reconfiguration capabilities. The device is built around three reconfigurable engines featuring different flavours and computation granularities that make it suitable for a wide range of signal processing application domains such as video coding, image processing, telecommunications, and cryptography. Performance of signal processing applications is evaluated from measurements performed on a CMOS 90 nm prototype. In order to characterize the application space of the processor, performance is compared with state-of-the-art devices, taking programmability, computational capabilities, and energy efficiency as the main metrics. The device exploits performance and energy efficiency significantly more than general purpose processors, while still maintaining a user-friendly programming approach that mainly relies on software-oriented languages. The device is able to achieve 1.2 to 15 GOPS with an energy efficiency from 2 to 50 GOPS/W when running the selected applications.

Dense matrix inversion is a basic procedure in many linear algebra algorithms. Any factorization-based dense matrix inversion algorithm involves the inversion of one or two triangular matrices. In this work, we present an improved implementation of a parallel triangular matrix inversion for heterogeneous multicore CPU/dual-GPU systems.

3D chip-to-chip capacitive interconnections are in common practice characterized with FEM solvers as they cannot be modeled as lumped RLC circuits as ohmic 3D interconnects. This paper describes some drawbacks of this procedure and proposes an innovative flow, based on post-layout parasitic extraction tools, to enable the designer to place capacitive interconnects as constrained macros in a digital design flow.

Dense matrix inversion is a basic procedure in many linear algebra algorithms. A computationally arduous step in most dense matrix inversion methods is the inversion of triangular matrices as produced by factorization methods such as LU decomposition. In this paper, we demonstrate how triangular matrix inversion (TMI) can be accelerated considerably by using commercial Graphics Processing Units (GPU) in a standard PC. Our implementation is based on a divide and conquer type recursive TMI algorithm, efficiently adapted to the GPU architecture. Our implementation obtains a speedup of 34x versus a CPU-based LAPACK reference routine, and runs at up to 54 gigaflops/s on a GTX 280 in double precision. Limitations of the algorithm are discussed, and strategies to cope with them are introduced. In addition, we show how inversion of an L- and U-matrix can be performed concurrently on a GTX 295 based dual-GPU system at up to 90 gigaflops/s.

In dermatology and in cosmetic science, the detailed analysis of the skin surface is still a key requirement to evaluate the effectiveness of medical or cosmetic treatments. Nowadays, the assessment of skin surface topographic structures such as wrinkles or micro-relief 3D profile is mainly obtained by profilometric analysis. Even though such an analysis gives a high level of detail, it is not suitable for in vivo studies since it requires the use of silicone cast replica of the skin. However, in the last few years a portable capacitive device has been proposed for in vivo skin topography characterization. This work presents the method we have developed to assess the capability of the capacitive device to provide reliable absolute measures of the skin surface structures. Extensive experiments carried out by comparing the measures achieved by means of the capacitive device and an optical profilometer allow us to validate our method.

Capacitive interconnections are very promising structures for high-speed and low-power signaling in 3D packages. Since the performance of AC links, in terms of Band-Width and Bit-Error-Rate (BER), depends on assembly and synchronization accuracy we performed a statistical analysis of assembly procedures and communication circuits. In this paper we present a yield prediction methodology for 3D capacitive links: starting from the analysis of communication circuits and BER measurements, we analyze stacking variability in order to predict reliability and performance. The proposed parametric yield analysis is demonstrated on a test-case, with constrained inter-electrode coupling and operating frequency.

The skin care retains a great importance for both aesthetics and health. Nowadays, many different approaches are known to quantify the skin health status by analyzing the skin appearance. However, most of these methods are still grounded on surface replicas, or on the use of devices that are not suitable for a routine approach. Also not all the methods are designed to achieve results in an automatic manner. The work presented here describes a method to extract an age-related feature from high resolution capacitive map of the human skin achieved by a portable device. Skin surface samples of 87 subjects have been analyzed in vivo and automatically through using wavelet decomposition. After that samples have been enhanced, we devised a feature, which correspond to the energy of the wavelet coefficients at the finest scale. Experiments prove that the feature we extracted is linearly related to skin ageing.

The application of microelectronics to bioanalysis is an emerging field which holds great promise. From the standpoint of electronic and system design, biochips imply a radical change of perspective, since new, completely different constraints emerge, while other usual constraints can be relaxed. While electronic parts of the system can rely on the usual established design-flow, fluidic and packaging design calls for a new approach which relies significantly on experiments. We make some general considerations based on our experience in the development of biochips for cell analysis.

In this letter, the implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation on a programmable architecture of a compression algorithm capable of encoding up to 20 black and white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The acquired images are then stored on a battery of on-chip flash memories that can be used to retrieve accident information to be used in legal confrontations. Having to perform in critical energy conditions (e.g., continued image acquisition for up to 10-20 s after an accident has occurred), the system was designed to minimize energy consumption at all levels. The system-on-chip has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25-/spl mu/m 6-metal standard-cell CMOS technology and works at 40 MHz with a 2.5-V power supply. Performance can be decreased to 12 QCIF frames/s, 24 MHz, and 1.3-V power supply in order to achieve 30-mW power consumption.

The complexity of the algorithms used in speaker verification is often not suitable for low power applications or HW platforms having small portions of memory available (smartcard). This paper presents a text-prompted recognition system composed of two blocks performing speaker verification and text confirmation. In both cases we made an effort to use low complexity HMM models of voiceprint and phonemes to be able to adopt strong simplification in probability computation. As far as the normalization process is usually the computationally most intensive process, we propose new efficient normalization techniques for both speaker verification and text confirmation. Low complexity is also achieved adopting smart quantization of features and model parameters. In spite of simplicity we report an Equal Error Rate (EER) of 1.2% for speaker verification and of 0.7% for text confirmation using 3 second speech utterances. Memory requirements are also kept small: less than 450 bytes are needed for speaker voiceprints.

A low-power feature extraction chip computing cepstral coefficients from linear predictive analysis on one-bit quantized speech signals is presented and its VLSI implementation is evaluated. An isolated-word small-vocabulary speech recognizer based on these features has been developed. Its recognition accuracy is within 2% below a system based on standard linear predictive cepstral features. The power consumption of the feature extractor chip is 30 /spl mu/W at 0.9 V.

We have designed and fabricated a low power IC to perform the inverse 8/spl times/8 DCT transform according to the CCITT precision specifications, suitable for portable video communication devices. Several design techniques have been used to reduce the power, such as a fast algorithm, an architecture that can exploit input signal correlation, and large amount of parallelism. The chip is fabricated in a triple metal 0.5 /spl mu/m gate array CMOS technology. The maximum throughput is 400 Kpix/s at 1.1 V, and 27 Mpix/s at 3.3 V. The measured power consumption is 35 /spl mu/W for typical image sequences in color QCIF format at 10 frames/sec with a 1.1 V power supply, making this device ideal for low power portable applications.

An algorithm for the linear interpolation of multi-input functions sampled on rectangular grids is presented. A geometric approach is adopted and the mathematics is thoroughly developed. We show that the algorithm is optimum. In fact, when the number n of inputs grows to infinity its computational requirement is O(n log n), which is the same as the lower-bound on the cost of continuous linear interpolation procedures.

This paper describes a fuzzy quality-controller for video coding systems based on the H.261 recommendation. The picture quality is tuned by a classification of the blocks of each frame of the sequence based on a simplified model of the human visual system. The quantization parameter is evaluated according to this classification making more relevant parts be coded with finer details at the expense of less significant regions. The system is based on a restricted number of fuzzy rules and can be easily reconfigured if a different classification criterion must be adopted. The subjective quality of coded sequences is better than the one obtained by the reference model at the cost of higher computational tasks.

This paper describes a VLSI array processor system that has been designed and built for classification problems based on the k-nearest neighbors approach. This architecture is suitable for different pattern recognition applications and is scalable to reduce the computation time. A prototype board with two processors has been built and a software driver has been written showing a speed up of 30 times over a software algorithm running on a Sun SPARC20 workstation.

This article presents a novel approach to the high-level system verification problem based on a hybrid hardware/software virtual emulation tool. Unavailable components or sub-systems are physically replaced on a prototype board by FPGAs whose electrical behavior is driven by software simulations of high-level description models. Such a prototype can smoothly evolve towards the final system as soon as the unavailable parts or the components under manufacturing become available. The simultaneous use of prototyping techniques such as field-programmable circuit boards with software simulation significantly improve the usefulness of our framework. A low-cost verification environment, with multiprocessing and multilanguage capabilities currently in use at University of Bologna, is described.

In this paper, a silicon compiler for analog fuzzy controllers is described. The layout is generated automatically, starting from global-system specifications accepted as a set of classical fuzzy rules involving fuzzy sets as well as numerical data, often available from numerical examples. The system relies on a library of basic cells designed using a CMOS n-well 0.7 /spl mu/m technology and on the use of Cadence software. Multi-inputs multi-outputs fuzzy logic-based controllers are synthesized, and the area and power requirements by any specific application are optimized. Some prototypes designed using the proposed methodology have been fabricated. For example, a two-inputs two-outputs fuzzy controller implementing a 2D rational function and a sinusoidal function requires, including the I/O circuitry, 1.9 mm/sup 2/ of silicon area, and the total power consumption is 44 mW at 5 V power supply. The maximum propagation delay, assuming a step input function, is 0.57 /spl mu/sec. The total computation time using a SUN Sparc2 Workstation is about 25 min, from specification of the expected behavior to layout.

The synthesis of fuzzy systems involves the identification of a structure and its specialization by means of parameter optimization. In doing this, symbolic approaches which encode the structure information in the form of high-level rules allow further manipulation of the system to minimize its complexity, and possibly its implementation cost, while all-parametric methodologies often achieve better approximation performance. In this paper, we rely on the concept of a fuzzy set of rules to tackle the rule induction problem at an intermediate level. An online adaptive algorithm is developed which almost surely learns the extent to which inclusion of a rule in the rule set significantly contributes to the reproduction of the target behavior. Then, the resulting fuzzy set of rules can be defuzzified to give a conventional rule set with similar behavior. Comparisons with high-level and low-level methodologies show that this approach retains the most positive features of both.

In this work we investigate techniques for embedding domain-specific spatial invariances into highly-constrained neural networks. This information is used to drastically reduce the number of weights which have to be determined during the learning phase, thus allowing us to apply artificial neural networks to problems characterized by a relatively small number of available examples. As an application of the proposed methodology, we study the problem of optical inspection of machined parts. More specifically, we have characterized the performance of a network created according to this strategy, which accepts images of parts under inspection at its input and issues a flag at its output which states whether the part is defective. The results obtained so far show that the proposed methodology provides a potentially relevant approach for the quality control of industrial parts, as it offers both accuracy and short software development time, when compared with a classifier implemented using a standard approach.

A low-power architecture for 2D-DCT is presented. It has been designed for portable H.261-compliant video-telephone applications, but most of the results and considerations apply to MPEG systems too. The presence of quantization in the coding process has been exploited, adapting the precision of DCT calculations to the quantization noise level. The proposed architecture has the capability of dynamically controlling power consumption by reducing the precision to the minimum required level and turning off sub-systems when they are not necessary for the computation. Compared with a standard implementation, power consumption is reduced by a factor between 7 and 10, without appreciable degradation of the transmission quality.

A simple form of cooperation between the k-nearest neighbors (NN) approach to classification and the neural-like property of adaptation is explored. A tunable, high level k-nearest neighbors decision rule is defined that comprehends most previous generalizations of the common majority rule. A learning procedure is developed that applies to this rule and exploits those statistical features that can be induced from the training set. The overall approach is tested on a problem of handwritten character recognition. Experiments show that adaptivity in the decision rule may improve the recognition and rejection capability of standard k-NN classifiers.

The two-dimensional massively parallel electromagnetic simulation program TEMPEST has been generalized to extend its applicability to many of the difficult problems in photolithography, metrology, and alignment. TEMPEST, which has been made available on the NCSA and other computing centers, combines together techniques for analysis of the transverse electric (TE) and the transverse magnetic (TM) polarizations, oblique incidence, highly dispersive materials, and a technique for synthesis of partially coherent optical images. The solution is based on the time-domain finite-difference method, but exploits the power of massively parallel computer architectures. Equations suitable for massively parallel implementation are given for oblique incidence, both polarizations and dispersive materials. Computer time per iteration cycle is constant irrespective of the polarization and angle of incidence. However, the total simulation time for convergence was found to be dominated by physical scattering phenomena. Convergence for the TM polarization is 1.5 times slower than the TE polarization because of edge currents, and oblique incidence is 2 times slower than normal incidence owing to artificial reflection from the domain boundaries. A typical simulation time is three to five minutes with 256 k (1 k=1024) simulation nodes on a CM-2 with 8 k processors. The effectiveness of the program for photolithographic applications is demonstrated by considering the effects of subtle changes in phase-shifting mask topography on the optical images.>

A new methodology for the minimization of a given set of fuzzy rules is presented. It is based on a novel mapping of fuzzy relations on Boolean functions and exploits existing Boolean synthesis algorithms. In this mapping each fuzzy membership predicate is translated into a Boolean variable and proper constraints on Boolean manipulations are added to guarantee fuzziness translation. The formal consistency of the approach depends on a fuzzy semantic which easily generalizes most of the existing models, granting broad applicability to the suggested procedure. The applicability of an enhanced two-level Boolean minimizer is demonstrated, and the technique is applied to the fuzzy identification of nonlinear systems, consistently reducing the number of rules and easing application of further optimization interventions.>

The authors describe the design and implementation of an application-specific digital architecture aimed at the solution in real time of the "K nearest neighbors" algorithm for classification problems, whose computational weight is very high. The system described here is an array-processor architecture in which the data base is split among several units that at the same time apply the same operations to different data stored in local memories. The sustained memory bandwidth of a system featuring 8 units is 2560 Mb/s and it provides a speed-up of 500 times over the software algorithm running on a SUN Sparc2 workstation.>

Classifiers based on the k-nearest neighbors (k-NN) approach have recently received an increasing attention because of their simple implementation and absence of training. In this technique, the similarity measure used to compute the distance between the stored patterns and the test element is the most crucial part of the method. The paper addresses this issue within the context of recognition of hand-written digits. A novel similarity measure is proposed and used to associate a number to each pair of samples in a suitable N-dimensional space in order to define the distance between two handwritten characters. The proposed similarity measure has been parameterized and the best values of these parameters have been evaluated using suitable statistical approaches. Finally, some results obtained from the classification of digits extracted from a ZIP code database are provided.>

A novel massively parallel technique for rigorous simulation of topography scattering in optical lithography has been developed and tested. The method is equivalent to the time-domain finite-difference method (TDFDM) used in electromagnetic scattering simulations, but exploits the parallel nature of wave propagation and the power of recent massively parallel architectures such as the Connection Machine. A working code called TEMPEST has been implemented on a Connection Machine CM-2 having 1 to 32 K processors with up to 1 M virtual processors. Numerical accuracy comparable with that of other fully rigorous methods was achieved. A very significant finding was that the solution required constant time per iteration for problems ranging from a few thousand unknowns up to one million, provided the ratio between the problem size and the number of processors is kept constant. The suitability of TEMPEST for solving a large class of topography structures important in alignment, metrology, and lithography is illustrated by examples.>

Based on a CGS (conjugate gradient squared) iteration with a partitioned natural ordering, a novel massively parallel algorithm for three-dimensional device simulation is presented. This algorithm requires constant time per matrix iteration independent of the number of grid nodes, and has convergence properties comparable to those of good algorithms currently used on sequential computers. This algorithm has been implemented on the Connection Machine and achieves supercomputer performance for large numbers of grid nodes. Results are presented for a wide variety of devices and mesh sizes.>

A discretization scheme is applied to the hydrodynamic model for semiconductor devices that generalizes the Scharfetter-Gummel method to both the momentum-conservation and the energy-conservation equations. The major advantages of the scheme are: (1) the discretization is carried out without neglecting any terms, thus providing a satisfactory description of such effects as velocity overshoot and carrier heating; and (2) the resulting equations lend themselves to a self-consistent solution procedure similar to those currently used to solve the simpler drift-diffusion equations. Two-dimensional steady-state simulations of an n-channel MOSFET and of an n-p-n BJT (bipolar junction transistor) have been carried out by means of an improved version of the program HFIELDS. Carrier-temperature plots have been obtained with a reasonable computational effort, demonstrating the efficiency of this technique. The results have been compared with those obtained with the standard drift-diffusion model and significant differences in the electron concentration have been found, especially at the drain end of the MOSFET channel.>

Etchant percolation through voids plays an important role in dissolution of radiation sensitive materials in IC manufacture, but analysis and simulation of this phenomenon are hampered by the complexity of carrying out simulations at up to 20000 voids etching simultaneously. An attempt is made to use a simplified material crack model and a formulation of the model in terms of cellular automata, which is well suited for massively parallel computation. Simulation is then used to characterize etch front propagation and the resulting resist profile shape. An analytic model predicting that the etch front velocity goes as a geometrical series in the product of crack density times the square of crack length shows agreement with the simulation results.>

An algorithm for three-dimensional capacitance evaluation suitable for parallel computers is proposed, and its implementation on a massively parallel architecture, the Connection Machine, is described. After a brief overview of the architecture and the programming style of the Connection Machine is given, a mathematical formulation of the general problem (i.e. the numerical solution of Laplace's equation in three dimensions) is reviewed. The numerical discretization scheme is described along with its implementation on a Connection Machine and the numerical performances of a set of examples are discussed. Experimental results show that this approach allows a fast and efficient solution for this type of problem.>

In this paper we propose a sensitivity-analysis technique for device design. By this method, we determine the linearized variations of the device terminal characteristics following some change either in the impurity distribution, or in device geometry, such as channel length and oxide thickness. This technique has been implemented in our general-purpose two-dimensional device-analysis program (HFIELDS) and proved to be very efficient, as only the assembly of the RHS and one back-substituton is required in order to achieve the final result. It is believed that the present method can be profitably used for both deterministic and statistical device design.