A method proposed for concurrent error detection in ALU's is used in the design of multiplier and divider arrays. This method, called recomputing with shifted operands (RESO), can detect all errors caused by failures confined to a cell of the cellular array. The assumption that the failures are confined to a small area of an integrated circuit and the precise nature of the failures is not known is very applicable to VLSI circuits. RESO uses time redundancy for error detection and requires only a small increase in the hardware of a multiply and divide array.

A new method of concurrent error detection in the Arithmetic and Logic Units (ALU's) is proposed. This method, called "Recomputing with Shifted Operands" (RESO), can detect errors in both the arithmetic and logic operations. RESO uses the principle of time redundancy in detecting the errors and achieves its error detection capability through the use of the already existing replicated hardware in the form of identical bit slices. It is shown that for most practical ALU implementations, including the carry-lookahead adders, the RESO technique will detect all errors caused by faults in a bit-slice or a specific subcircuit of the bit slice. The fault model used is more general than the commonly assumed stuck-at fault model. Our fault model assumes that the faults are confined to a small area of the circuit and that the precise nature of the faults is not known. This model is very appropriate for the VLSI circuits.