Ternary reversible logic functions are generally represented as ternary Galois field sum of products (TGFSOP) expressions and the TGFSOP expressions are mapped to reversible circuits using cascades of Feynman and Toffoli gates. Although a ternary logic function with a large number of variables can be minimized as a TGFSOP expression, the process is computationally expensive and the resulting reversible circuit tends to have a high quantum cost and ancilla inputs. To overcome these limitations, in this work we propose a new method of representing ternary reversible logic functions as Max of Min-terms (Max-Min) expressions, which can be mapped to a reversible circuit using multiple-controlled unary gates requiring lower quantum cost and fewer ancilla inputs. We propose a map-based minimization method for Max-Min expressions of up to four variables focusing on restrictions of the reversible circuit mapping technique.

Ternary reversible circuits are normally realized as Toffoli cascades using ternary Galois field sum of products (TGFSOP) expressions. In this work we propose a new method for realization of ternary reversible circuits using ternary Max-Min expressions. The proposed method uses ternary multiple-controlled unary gates to map Max-Min expression into reversible circuit. We also present techniques for realizations of multiple-controlled unary gates using M-S gates at the quantum level. Preliminary results show that the proposed method produces better results than TGFSOP-based method in terms of both quantum cost and ancilla inputs.

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using emerging technologies such as quantum dot cellular automata. Earlier work uses traditional designs for sequential circuits and replaces the flip-flops and the gates with their reversible counterparts. Our earlier work used a direct feedback method without any flip-flops, which proved to be better than the replacement technique in terms of both quantum cost and ancilla inputs. This work is an improved version of our direct feedback method, which uses a different approach to the reversible mapping of sequential circuits. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs.

Reversible logic has been suggested as one solution to the problem of power consumption in today's electronic devices. This paper addresses the issue of designing reversible latches and provides an overview and analysis of some proposed designs.

A new technique that makes use of a systolic array structure is proposed for solving the common approximate substring (CAS) problem. This approach extends the technique introduced in (Kent et al., 2006) from the computation of the edit-distance between two strings to the more encompassing CAS problem. The technique presented is validated and analyzed through simulation

Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. We present an analysis of a basic memory element, the RS-latch, and a number of possible implementations. We then go on to introduce four reversible flip-flop designs based on the reversible RS-latch implementation

An implementation of an algorithm for string matching, commonly used in DNA string analysis, using configurable technology is proposed. The design of the circuit allows for pipelining to provide a performance increase. The proposal is unique in that we suggest a design that is specific to certain parameters of the problem, but may be reused for any particular instance of the problem that matches these parameters. The use of a field programmable gate array allows the implementation to be instance specific, thus ensuring maximal usage of the hardware. Analysis and preliminary results based on a prototype implementation are presented.

There are many computationally intensive problems in the area of digital design and logic synthesis. Some of these have no "good" solution; that is, simply by their definition they have exponential run-times. In order to overcome this, we examine the possibility of a configurable hardware solution to speed up one such problem. The computation of the problem is carried out on a Field Programmable Gate Array (FPGA), where the problem is encoded in such a way that within certain parameters, the design of the solution need not be changed for working with a variety of benchmark circuits. This saves considerably on compilation and configuration times. The use of configurable hardware, however, still allows for reconfiguration in situations where the parameters change significantly enough to require an altered approach. We examine two implementations of the problem, which in this case consists of computing the autocorrelation coefficients for a Boolean function.

Four operations on switching functions are used to define a classification technique based on the autocorrelation function. The relationship between these classes and the well-known spectral classes is investigated, and a canonical representative for each class is proposed. It is thought that these classes will be of use in logic synthesis employing decision diagram representations for intermediate steps.