This paper first highlights the mathematical properties of 128-bit AES encryption and decryption, and then uses these properties to develop a freeware, high-throughput, parallel implementation of the AES algorithm for resource-limited hardware. We compare our throughput results to advertised industry data throughput rates for comparable hardware settings. Our core can be utilized in various applications of 128-bit AES encryption and decryption. Different potential modes of operation for 128-bit AES were analyzed with respect to advantages and disadvantages in practical network settings, with a focus on Asynchronous Transfer Mode (ATM) networks.

An efficient parallel implementation of the robot inverse dynamics based on the recursive Newton-Euler formulation is considered. The algorithm basically partitions the computations related to a manipulator link among separate processors, resulting in a parallel architecture in which the number of processors equals the number of degrees of freedom of the manipulator. This has considerably low inherent parallelism if the forward propagation of velocities and accelerations and the backward propagation of forces and torques are synchronized. Therefore, in order to maximize the parallelism, the synchronization is completely removed, leaving each processor on the most recent values of the propagated variables. Since the mathematical approach for error analysis is too complex and the simulation approach is incomplete and unreliable, the algorithm is investigated on a real, multiprocessor machine, KUMARAN. A series of experiments with the model of the PUMA 560 manipulator and randomly generated inputs has shown surprisingly small errors. Some improvements of the algorithm which do not impair the time efficiency but provide further reduction of the approximation error are presented.>

Abstract There are two principal methods used to exploit the parallelism available on a parallel machine: the program to be executed can be optimized by hand, or the program can be automatically converted to parallel machine code by a compiler. The first method usually derives parallelism at the procedure level; a parallel program is written in a high‐level language and typically has various modules executing in parallel. By contrast, the compiler methodically transforms the program into parallel code using various transformations, such as code movement. The automatic conversion of a program to parallel code is called compaction or parallelization. This paper describes the evolution of a new compaction program and presents a new algorithm for determining legal code movements. A simulator of the target architecture was used to estimate the execution times of a sample suite of programs before and after compaction. The results verify that substantial advantages arise from applying this compaction technique.