Demo Data from VLDB 2026 / reviewers in the wild / expert
Tohru Matsunaga
dblp:85/703
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 1998
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
2 papers |
Optical networks · 68% Internet architecture and protocols · 27% Routing and switching · 4% |
Topics — the 3 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols › ATM networks
ATM switch |
0.0 | 1 | 1998 | Optical output buffered ATM switch prototype based on FRONTIERNET architecture · IEEE J. Sel. Areas Commun. 1998 |
Optical networks › optical switching
optical packet switching |
0.0 | 1 | 1998 | Optical output buffered ATM switch prototype based on FRONTIERNET architecture · IEEE J. Sel. Areas Commun. 1998 |
Optical networks › optical switch
optical switch architecture |
0.0 | 1 | 1998 | Optical output buffered ATM switch prototype based on FRONTIERNET architecture · IEEE J. Sel. Areas Commun. 1998 |
Methods — techniques the papers use, named apart from their topics
output-buffering scheme · 0.0simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1998 | Optical output buffered ATM switch prototype based on FRONTIERNET architectureabstractWe constructed a rack-mounted prototype photonic ATM switch based on the FRONTIERNET architecture. The advantages of the architecture are that its output-buffering scheme overcomes the bottlenecks that can occur when receiving and storing concurrent high-speed cells, and that there is no need to deal with contention resolution between input highways. The prototype has 16 input/output ports and 2.5 Gb/s transmission speed. Actually, six input ports and one output port are mounted in two racks. We demonstrated successful cell routing and buffering, and its stable operation, with 24-h bit-error-free switching operation. We also discussed problems to be solved in increasing the throughput of FRONTIERNET. Yoshiaki Yamada, Koji Sasayama, Keishi Habara, Akira Misawa, Masato Tsukada, Tohru Matsunaga, Ken-ichi Yukimatsu |
IEEE J. Sel. Areas Commun. | 6 |
| 1997 | Design of Photonic ATM Switch and a Rack-Mounted PrototypeabstractThis paper describes large-capacity photonic ATM switching systems being developed that use FDM (or WDM) techniques. Our system is based on a simple star architecture with a modular structure. We show that it is possible to obtain a 320-Gb/s system that has enough S/N margin and can tolerate the polarization and frequency dependencies of optical devices. Our experiments using rack-mounted prototype modules to demonstrate the feasibility of our system, as well as successful 10-Gb/s 4/spl times/4 broadcast-and-select and 2.5-Gb/s 16/spl times/16 frequency-routing switch operations. Tohru Matsunaga, Keishi Habara, Akira Misawa, Yoshiaki Yamada, Toru Okugawa, Masato Tsukada, Shigeki Hino, Koji Sasayama, Ken-ichi Yukimatsu |
ICC (3) | 1 |
| 1993 | Sorting-based routing algorithms of a photonic ATM cell switch: HiPowerabstractHiPower is a photonic ATM switch having a two-layered structure, consisting of an electrical control layer and an optical transport layer, realized by a detouring hypercube interconnection network structure. Four sorting-based routing algorithms suitable for high-speed hardware control of HiPower are proposed. They are evaluated by computer simulations in terms of delay and cell loss in the switch under uniform traffic distribution. The simulation results suggest that all four methods are acceptable in their traffic characteristics and that the DD method, in which the cell nearest to its destination is given the highest priority in routing, seems to be the most attractive from the hardware implementation viewpoint. It is also confirmed that subpriority sorting based on the number of detourings reduces the delay variance. Simulation results proving that the detouring hypercube network is a practical and powerful architecture for a two-layered ATM cell switch, thus, the HiPower providing high throughput, are given.> Tohru Matsunaga |
IEEE Trans. Commun. | 1 |