An 81 MSamples/s JPEG 2000 single-chip encoder is implemented on 5.5 mm/sup 2/ area using 0.25-/spl mu/m CMOS technology. This IC can losslessly encode HDTV 720p resolution at 30 frames/s in real time. Three techniques are adopted: line-based discrete wavelet transform, parallel embedded block coding, and precompression rate-distortion optimization. The line-based discrete wavelet transform achieves the minimum external memory access, while the internal memory is reduced by a proper memory access scheme. The parallel embedded block coding increases the throughput and reduces the memory bandwidth with similar hardware cost comparing to conventional architectures. By accurately estimating bit rates, the precompression rate-distortion optimization reduces the required computational power and processing time of the embedded block coding since the code-blocks are truncated before compression. Experimental results show that this encoder has the highest throughput with the smallest area compared with other designs in the literature.

This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC algorithm. By processing all the bit planes in parallel, the state variable memories for the context formation (CF) can be completely eliminated. The length of the FIFO (first-in first-out) between the CF and the arithmetic encoder (AE) is optimized by a reconfigurable FIFO architecture. To reduce the hardware cost of the parallel architecture, we proposed a folded AE architecture. The parallel EBC architecture can losslessly process 54 MSamples/s at 81 MHz, which can support HDTV 720p resolution at 30 frames/s.

In this paper, a novel rate control algorithm suitable for real-time video encoding is proposed. The proposed algorithm uses mean absolute error (MAE) results of motion estimation (ME) to achieve bit-rate control. Neither pre-analysis nor multi-pass encoding is required in our algorithm, which makes real-time hardware implementation possible. A new hardware oriented scene change detection method is also included in this rate control framework to achieve better video quality. Experiments show our rate control algorithm behaves well in all situations. The hardware architecture for this algorithm is also described. Implementation shows our proposed algorithm can be efficiently integrated into a low cost, high efficiency video encoder.

In the new video coding standard, MPEG-4 AVC/JVT/H.264, motion estimation is allowed to use multiple reference frames. The reference software adopts a full search scheme, and the increased computation is in proportion to the number of searched reference frames. However, the reduction of prediction residues is highly dependent on the nature of the sequences, not on the number of searched frames. We present a method to speed up the matching process for multiple reference frames. For each macroblock, we analyze the available information after intra prediction and motion estimation from the previous frame to determine whether it is necessary to search more frames. The information we use includes selected mode, inter prediction residues, intra prediction residues, and motion vectors. Simulation results show that the proposed algorithm can save up to 90% of unnecessary frames while keeping the average miss rate of optimal frames less than 4%.

H.264 is initiated by ITU-T as H.26L and will become a joint standard of ITU-T and MPEG. The coding complexity of H.264 is much higher than MPEG-4 simple profile and advance simple profile algorithms. In order to achieve real-time encoding, hardware implementation is required. The original test model of H.264 (JM) is designed to achieve high coding performance. Some algorithms of the test model require lots of operations with little coding efficiency improvement. And some algorithms create data dependencies that prevent parallel hardware accelerations. This paper presents analysis of the H.264 video coding algorithm from a hardware-oriented viewpoint. Intra prediction, Hadamard transform and motion estimation algorithms are reviewed and modified to a hardware friendly configuration. The rate distortion penalties of these modifications are simulated and shown in this paper.

In this paper, a novel rate control algorithm suitable for realtime video encoding is proposed. The proposed algorithm uses mean absolute error (MAE) results of motion estimation (ME) to achieve bitrate control. Neither pre-analysis nor multi-pass encoding is required in our algorithm, which makes realtime hardware implementation possible. A new hardware oriented scene change detection method is also included in this rate control framework to achieve better video quality. Experiment shows our rate control algorithm behaves well in all situations. Hardware architecture for this algorithm is also described. Implementation shows our proposed algorithm can be efficiently integrated into low cost, high efficiency video encoder.

In this work, a novel word-level algorithm of the embedded block coding in JPEG 2000 is proposed. Unlike conventional approaches, all bitplanes of coefficients are processed in parallel in the proposed algorithm. The algorithm is based on the observations and the analysis of the significant state of a coefficient and its contribution to neighbors. As a result of the analysis, there is only the coding pass of the MSB of a coefficient is the required information for the word-level processing. An algorithm for finding the coding pass of the MSB of a coefficient is also proposed. The number of scans of the entire code block is reduced to two scans and is independent of the number of bit planes.

This paper presents an efficient VLSI architecture for the deblocking filter in H.264/JVT/AVC. We use an array of 8/spl times/4 8-bit shift registers with reconfigurable data path to support both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Two SRAM modules are carefully organized not only for the storage of current macroblock data and adjacent block data but also for the efficient access of pixels in different blocks. Simulation results show that under 0.25 /spl mu/m technology, the synthesized logic gate count is only 19.1 K (not including a 96/spl times/32 SRAM and a 64/spl times/32 SRAM) when the maximum frequency is 100 MHz. Our architecture design can easily support real-time deblocking of 720p (1280/spl times/720) 30 Hz video. It is valuable for platform-based design of H.264 codec.

In the new video coding standard, MPEG-4 AVC/JVT/H.264, motion estimation is allowed to use multiple reference frames. The reference software adopts full search scheme, and the increased computation is in proportion to the number of searched reference frames. However, the reduction of prediction residues is highly dependent on the nature of sequences, not on the number of searched frames. In this paper, we present a method to speed up the matching process for multiple reference frames. For each macroblock, we analyze the available information after intra prediction and motion estimation from previous one frame to determine whether it is necessary to search more frames. The information we use includes selected mode, inter prediction residues, intra prediction residues, and motion vectors. Simulation results show that the proposed algorithm can save up to 90% of unnecessary frames while keeping the average miss rate of optimal frames less than 4%.

H.264 [Committee Draft of Joint Video Specification, July 2002] is initiated by ITU-T as H.26L and will become a joint standard of ITU-T and MPEG. The coding complexity of H.264 is much higher than MPEG-4 simple profile and advance simple profile algorithms. In order to achieve real-time encoding, hardware implementation is required. The original test model of H.264 (JM) [Joint Video Team, August 2002] is designed to achieve high coding performance. Some algorithms of the test model require lots of operations with little coding efficiency improvement. And some algorithms create data dependencies that prevent parallel hardware accelerations. This paper presents analysis of H.264 video coding algorithm in a hardware-oriented viewpoint. Intra prediction, Hadamard transform and motion estimation algorithms are reviewed and modified to a hardware friendly configuration. The rate distortion penalties of these modifications are simulated and shown in this paper.

In this paper, a novel video transmission architecture is proposed to meet the low-delay and error robust requirement of wireless video communications. This architecture uses FEC coding and ARQ protocol to provide efficient bandwidth access from wireless link. In order to reduce ARQ delay, a video proxy server is implemented at the base station. This video proxy not only reduces the ARQ response time but also provides error tracking functionality. We use H.263 as the experimental platform for our architecture. Experiments show that average luminance PSNR decreases only 0.35db for the "Foreman" sequence under a random error condition of 10/sup -3/ error probability.

Video communications over wireless networks often suffer from various errors. A novel video transmission architecture is proposed to meet the low-delay and error-robust requirement of wireless video communications. This architecture uses forward error correction coding and automatic repeat request (ARQ) protocol to provide efficient bandwidth access from wireless link. In order to reduce ARQ delay, a video proxy server is implemented at the base station. This video proxy not only reduces the ARQ response time, but also provides error-tracking functionality. The complexity of this video proxy server is analyzed. Experiment shows that about 8.9% of the total macroblocks need to be transcoded under a random-error condition of 10/sup -3/ error probability. Because H.263 is the most popular video coding standard for video communication, we use it as an experiment platform. A data-partition scheme is also used to enhance error-resilience performance. This architecture is also suitable for various motion-compensation-based standards like H.261, H.263 series, MPEG-1, MPEG-2, MPEG-4, and H.264. For "Foreman" sequence under a random-error condition of 10/sup -3/ error probability, luminance peak signal-to-noise ratio decreases only 0.35 dB, on average.

In this paper, a low-power full-search block matching (FSBM) motion-estimation design for the ITU-T recommendation H.263+ standard is proposed. New motion-estimation modes in H.263+ can be fully supported by our architecture. Unlike most previously presented motion-estimation chips, this design can deal with 8/spl times/8 and 16/spl times/16 block size with different searching ranges. Basically, the proposed architecture is composed of an integer pixel unit with 64 processing elements, and a half-pixel unit with interpolation, a control unit, and data registers. In order to minimize power consumption, gated-clock and dual-supply voltages are used. This design has been realized by TSMC 0.6 /spl mu/m SPTM CMOS technology. The power consumption is 423.8 mW at 60 MHz and the throughput is 36 fps in CIF format.

Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy to extend. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform and the mirror-extension is realized via the routing network. This design has been implemented and fabricated in a 0.35 /spl mu/m 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 /spl mu/m/spl times/2500 /spl mu/m. For a 256/spl times/256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. Hence the proposed architecture is suitable for real-time applications such as JPEG 2000.