A new subscriber communication system and its design philosophy are described. In addition to telephone communication, the system is simultaneously able to offer data communication, still picture communication, etc. The system is composed of a packetized voice/data terminal, a multi-service switching equipment and the digital subscriber loop connecting between them. The system utilizes the existing subscriber line efficiently and is entirely suitable for coming telephone and data public digital network. 64 kbit/s PCM coded voice conversation and 48 kbit/s data communication were achieved simultaneously over 96 kbit/s digital subscriber line which was spanned up to 2 km.

In this paper, a new digital signal processing algorithm for the digital TDM-FDM translator is proposed. The digital TDM-FDM translator, which performs a direct translation between two multiplex formats in the telephone network (time-division-multiplexing (TDM) and frequency-division-multiplexing (FDM)) by using digital techniques, has advantages in accuracy and stability of characteristics over equivalent analog equipments. However from the economical point of view, it largely depends on the cost reduction of semiconductor devices and LSI technologies. The proposed algorthm can be realized using only two digital filters and does not require product modulators or Fast Fourier Transform (FFT) processors. The required number of multiplications, which is closely related to the quantity of hardware, is considerably reduced by the multistage structure of this algorithm. The reduction in the kind of required digital hardware and the required number of multiplications makes it possible to efficiently utilize the new hardware realization techniques of digital filters or multipliers using read-only memories and simple logic devices. Since it is foreseen that cost reduction of memory devices will be more rapid than that of logic devices, the proposed algorithm is expected to be advantageous with regard to cost over existing algorithms where complex multiplier logic is required. The estimation of the computation rate is carried out with reference to a practical case. The computer simulation results are also shown.