This article presents hardware-efficient harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation, targeted for the dynamic characteristic testing of high-resolution 14-bit and 16-bit 1 MS/s analog-to-digital converters (ADCs) in VLSI testing environments. For 14-bit ADC testing, a single 16-bit digital-to-analog converter (DAC) with a simplified DPD circuit is demonstrated to achieve a second-order harmonic distortion (HD2) level of −92dBc. For 16-bit ADC testing, where higher resolution is required, we propose a novel dual-DAC architecture utilizing a dual-range synthesis method to enhance effective resolution and suppress harmonics up to the fifth-order (HD2–HD5). Furthermore, to minimize the hardware overhead in practical implementations, we introduce optimized field-programmable gate array (FPGA) design strategies, including time-division multiplexing (TDM) and compressed sine look-up tables (LUTs), achieving a 96.8% reduction in memory usage. The parameters are extracted via a single-step, deterministic calibration flow, ensuring high testing throughput without iterative optimization. Experimental results show HD2–HD5 levels down to −120 dBc, providing a hardware-efficient solution for high-precision built-out self-test (BOST) and future system-on-chip (SoC) integration.

This paper presents a 10ps-order flexible resolution time-to-digital converter (TDC) consisting of only Lookup Tables and Flip-Flops that can be applied to legacy FPGAs, which is industry friendly. The proposed TDC is a Vernier delay-line based TDC. By using MUX chains as the delay adjustable buffers, it realizes flexible and high resolution 10ps-order TDC. By controlling the control values of each MUX chain independently, the nonlinearity of TDC is compensated. In the evaluation using the AMD Artix-7 FPGA, the DNL and INL were [−0.26 LSB, 0.91 LSB] and [−0.84 LSB, 2.27 LSB], respectively, at a resolution of 8.92 ps.

This paper introduces a highly reliable delay-based weak FPGA Physically Unclonable Function (PUF), leveraging stochastic delay measurement with PLLs. The delay of delay-lines is precisely measured using the proposed fully synchronous stochastic delay measurement method. Thus, the reliability surpasses that of conventional PUFs that depend on asynchronous circuits or measurement. In the evaluation, the inter-chip HD of the proposed PUF without Spread Spectrum Clock Generator (SSCG) is 47.79%, and the intra-chip HD is 0.0052%, which is about 1/100 of the conventional PUFs. With SSCG, the inter-chip HD of the proposed PUF is 47.98%, and the intra-chip HD is 0.00092%, which is about 1/5 of the value in the absence of SSCG.

This paper presents a physically unclonable function (PUF) using flash time-to-digital converter (TDC) with linearity self-calibration. The proposed PUF utilizes that the variation of delay of delay elements of TDC is unique to the device and unclonable. The proposed PUF is constructed using the flash TDC with linearity self-calibration using histogram method. With the linearity self-calibration operation, variation of delay elements is estimated. The response output of the PUF is calculated using the estimated variation and the challenge inputs. The proposed PUF is a simple digital circuit consisting of basic digital elements. It is easy to design and implement to both SoC and FPGA. It can be used as not only strong PUF but also as a TDC with fine linearity. The experimental results with Artix7 FPGA show that the intra-chip variation is 8.9 % and the inter-chip variation is 46.9 %. The probability of the correct identification is 99.8 %. Extra resources to construct the proposed PUF are 33.7 % of the resources of the TDC with linearity self-calibration.

This paper describes two harmonics cancellation techniques using digital predistortion (DPD) for low-distortion sinusoidal signal generation with direct digital synthesizer; it is targeted for the dynamic characteristic testing of 14-bit and 16-bit 1MS/s ADCs and their testing sinusoidal wave frequencies are around 100kHz. (i) The first one is an analog-intensive DPD method for the 16-bit ADC testing. The HD2 and HD3 of the original sinusoidal signal are measured with FFT method, and then their 180-degree phase-shifted signals are generated with an auxiliary DAC and added to the original signal to cancel the HD2 and HD3. Our experiments show that −120dBc of HD2 and HD3 can be achieved. (ii) The second one is a digital-intensive DPD method for the 14-bit ADC testing. The digital data of the 180-degree phase-shifted signals of the measured HD2 and HD3 are added to the original digital data of the direct digital synthesizer. The circuit is simple, and our experiments show that −92dBc of HD2 can be achieved. Their details of analysis, simulation and experimental results are shown.

This paper demonstrates that a 20-bit subrange ADC for high precision voltage measurement can be implemented with standard ATE resource and BOST circuits, without special devices. Our prototype 20-bit ADC employs subranging architecture and consists of a 16bit ADC (LTC1867), a 20-bit DAC (ADC5791), Arduino and some additional circuits. Its operation has been confirmed with simulations and experiments, and effects of non-idealities for each circuit to the overall 20-bit ADC performance have been evaluated. We consider that a 16bit audio-band digitizer in an ATE system can be used as the 16bit ADC while the 20-bit DAC as well as an error amplifier (another component for the subranging ADC) can be implemented with BOST circuits.

Testing of analog circuits plays a very important role in achieving both reliability and low cost for IoT and automotive systems. It is a technological challenge including circuit design, signal processing algorithms and measurement methods. This session consists of three talks from industry and academia in this area.

This paper presents a theoretical analysis of the stochastic calibration of TDC using two ring oscillators. Designers of TDC with the calibration function have to decide the design parameters to guarantee the convergence of error and valid calibration time. The basic theory of the calibration is useful to decide these parameters and the policy on the calibration design. The performance of the stochastic calibration depends on the design parameters, the frequencies of the two ring oscillators, the number of the stages, the buffer delay, and so on. This work analyzes explicitly the relation between these parameters and the performance of the calibration with simulation-based analysis. Simulation results reveal that the convergence of the calibration is guaranteed when both of the cycles of the two ring oscillators are the prime cycles. The histogram of each bin converges to the corresponding buffer delay value in a well-behaved manner, the DNL measurement error decreases monotonically in proportion to the increase of the number of the times of the measurement. In other words, the required number of the measurement times is in proportion to the required accuracy of calibration. This result is applied to the calibration of VDL-based TDC, too.

This paper describes a digital method of reducing timing mismatch effects in time-interleaved ADCs used in ATE systems: we use cross-correlation among channel ADC outputs to detect channel timing skew, and make successive-approximation adjustments to our proposed linear-phase-digital delay filter to compensate for the timing skew. Simulation results validate the effectiveness of the proposed method. We found that using multitone input signals with cross-correlation of outputs provided a more robust way of detecting timing skew than using a singletone input signal. Since our proposed approach is fully digital, it is reliable, and suitable for fine CMOS implementation.

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The pro- posed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18-μm process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average.

This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54%. It is 6.62% smaller than the conventional method, and 8.41% larger than standard scan design.

This paper proposes a delay measurement technique using signature registers, and a scan design for delay measurement utilizing the proposed delay measurement technique to detect small-delay defects. The delay of circuits can be measured with the scan design with lower area, smaller data volume, and shorter measurement time than with the conventional scan design for delay measurement. Accordingly, the small-delay defects outside the range of the normal-distributed delay are detected with lower cost. Evaluation with 0.18 ¿m process shows that the area overhead of the proposed scan design is 32.2% smaller than that of the conventional method. The measurement time and the data volume for the measurement are reduced 66.7% and 66.0% compared with the conventional method, respectively.

This paper proposes a BIST (built-in self test) method for testing the PEs (processing elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (linear feedback shift register) and MISR (multiple input signature register) as DFT (design for testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-I, a coarse grained dynamically reconfiguration processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead

In this paper, a new design for online testing of system on a chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which keeps its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances.