This paper presents a full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver designed to overcome the switching supply noise (SSN). The signal-to-noise ratio (SNR) is impacted mainly by transmitter echo signal, inter-symbol interference (ISI), SSN, etc. This paper primarily focuses on comparing the impact of SSN on the transceiver. In general, the voltage mode (VM) transmitter injects more SSN compared to the current mode (CM) transmitter. To address this, the proposed architecture combines voltage mode source series terminated (VM-SST) and current mode logic (CML) transmitters to improve SNR by mitigating the effect of SSN. In addition, this paper proposed a passive R-Gm hybrid for linear and energy-efficient subtraction of the transmitted signal and extracting the received signal. Implemented in TSMC-65 nm CMOS technology for a link with 3 dB insertion loss at 5 GHz Nyquist frequency, the simulated results of the proposed architecture improve the eyeopening by 30% at 10+10 Gb/s SBD data rate.

This paper presents a current mode (CM) replica driverless full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver for chip-to-chip interconnect. For FD-SBD signaling a hybrid architecture is used to extract the received signal from the channel by canceling the transmitted signal. However, the pin package parasitics at the interface increases the near-end reflection and increases the cancellation error which reduces the received signal eye opening. Reducing the cancellation error by using filters increases the power consumption along with the complexity. In the case of single-ended full-duplex signaling with dedicated wires for transmitting and receiving, the received signal eye opening is affected significantly by the cross-talk and power supply noise. Therefore, in this work a hybrid of differential and common mode signaling is used to reduce the cancellation error and common-mode noise to increase the data rate. The proposed transceiver does not require an additional replica driver to retrive the received signal unlike conventional transceivers. The architecture is designed using 65 nm CMOS technology for a 7.5-inch channel with 6.46 dB insertion loss at 5 GHz Nyquist frequency. An aggregate full-duplex data rate of 30 Gb/s with an energy efficiency of 0.43 pJ/b is achieved in this work.

Real-time modulation recognition is crucial for modern communication systems in various cognitive radio tasks. While prior works have employed deep learning techniques to address this challenge, few are feasible for real-time applications. Spiking Neural Networks (SNNs) present a promising alternative to conventional deep learning approaches, enabling low-power hardware implementations. However, existing SNN-based modulation recognition methods often lag behind traditional techniques or necessitate high sample rate implementations. This work introduces an SNN architecture that utilizes a low-resolution quantizer in the receiver and operates at a lower rate than the quantizer, resulting in significant area and power savings when integrated into a system. We experimentally determine the optimal quantizer resolution and the ratio of quantizer-to-SNN rate. The optimized network achieves an average classification accuracy of 68.45% on the RadioML2018.01A dataset, utilizing a 4-bit quantizer and running at a rate 16 times lower than the quantizer. This performance is comparable to conventional neural networks and surpasses that of previous spiking-based methods, especially at low signal-to-noise ratio (SNR) conditions.

This paper presents a single-ended voltage-mode (VM) simultaneous bidirectional (SBD) transceiver for chip-to-chip interconnects. A hybrid network in the receive path cancels the transmitted signal to extract the received signal enabling SBD signaling. The conventional source-series terminated (SST) and trans-impedance amplifier (TIA)-based transmitters used in the SBD signaling transceivers consume high power to minimize output impedance variation. The proposed design minimize this variation with low power consumption, thereby leading to a low-power transceiver. In addition, the power consumption while incorporating feed-forward equalizer (FFE) is reduced by using current-mode implementation in the proposed transceiver. Implemented using TSMC PDK in 65 nm technology, the simulation results gives an energy efficiency of 0.35 pJ/b at 20 Gb/s SBD data-rate.

Reservoir computing (RC) significantly reduces the requirement on hardware and training resources, making it suitable for edge-computing applications. This work proposes using voltage-controlled oscillator (VCO)-based spiking neurons for RC to leverage the intrinsic randomness and variability of the neuron circuit for low-power operations. We describe the underlying circuit design and propose a network architecture based on the spiking neuron for RC. We demonstrate the effectiveness of the proposed RC network using VCO-based spiking neurons through benchmark tasks and electrocardiogram (ECG) classification.

In this paper, a ring-oscillator (RO) based sub-1V leaky integrate-and-fire (I&F) neuron circuit is proposed, that can support user programmable refractory period and spike-frequency adaptation. Designed in CMOS 65-nm TSMC process, the neuron can operate from 0.9 V and has the unique feature that the same circuit can be programmed to operate either at biological time-scales or at accelerated time-scales. As ring-oscillators in nanometer CMOS are small compared to capacitors used in existing I&F silicon neuron (SiN), a large number of RO-based neurons can be integrated along with complex digital circuits to realize a single-chip Neuromorphic-SoC.