Justin Teller

dblp:86/1882 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorDatabases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Storage systems · 48% Energy-efficient computing · 16% Processor architecture and microarchitecture · 16%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › data compression
time series compression
0.212015
Gorilla: A Fast, Scalable, In-Memory Time Series Database · Proc. VLDB Endow. 2015
Storage systems › data management
time series database
0.212015
Gorilla: A Fast, Scalable, In-Memory Time Series Database · Proc. VLDB Endow. 2015
Processor architecture and microarchitecture
many-core architecture
0.212013
Runnemede: An architecture for Ubiquitous High-Performance Computing · HPCA 2013
Energy-efficient computing › voltage scaling
near-threshold voltage operation
0.212013
Runnemede: An architecture for Ubiquitous High-Performance Computing · HPCA 2013
Memory systems
on-chip memory
0.212013
Runnemede: An architecture for Ubiquitous High-Performance Computing · HPCA 2013
Storage systems
storage reliability
0.112015
Gorilla: A Fast, Scalable, In-Memory Time Series Database · Proc. VLDB Endow. 2015

Methods — techniques the papers use, named apart from their topics

simulation · 0.2hardware-software co-design · 0.2
YearPublicationVenuePosition
2015 Gorilla: A Fast, Scalable, In-Memory Time Series Database
abstract
Large-scale internet services aim to remain highly available and responsive in the presence of unexpected failures. Providing this service often requires monitoring and analyzing tens of millions of measurements per second across a large number of systems, and one particularly effective solution is to store and query such measurements in a time series database (TSDB). A key challenge in the design of TSDBs is how to strike the right balance between efficiency, scalability, and reliability. In this paper we introduce Gorilla, Facebook's in-memory TSDB. Our insight is that users of monitoring systems do not place much emphasis on individual data points but rather on aggregate analysis, and recent data points are of much higher value than older points to quickly detect and diagnose the root cause of an ongoing problem. Gorilla optimizes for remaining highly available for writes and reads, even in the face of failures, at the expense of possibly dropping small amounts of data on the write path. To improve query efficiency, we aggressively leverage compression techniques such as delta-of-delta timestamps and XOR'd floating point values to reduce Gorilla's storage footprint by 10x. This allows us to store Gorilla's data in memory, reducing query latency by 73x and improving query throughput by 14x when compared to a traditional database (HBase)-backed time series data. This performance improvement has unlocked new monitoring and debugging tools, such as time series correlation search and more dense visualization tools. Gorilla also gracefully handles failures from a single-node to entire regions with little to no operational overhead.
Tuomas Pelkonen, Scott Franklin 0002, Paul Cavallaro, Justin Meza, Justin Teller, Kaushik Veeraraghavan
Proc. VLDB Endow.6
2013 Runnemede: An architecture for Ubiquitous High-Performance Computing
abstract
DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously. Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption. Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks. We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture.
Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard A. Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh
HPCA15
2009 Scheduling tasks on reconfigurable hardware with a list scheduler
abstract
In this paper, we propose a static (compile-time) scheduling extension that considers reconfiguration and task execution together when scheduling tasks on reconfigurable hardware, designated as Mutually Exclusive Groups (-MEG), that can be used to extend any static list scheduler. In simulation, using -MEG generates higher quality schedules than those generated by the hardware-software co-scheduler proposed by Mei, et al. and using a single configuration with the base scheduler. Additionally, we propose a dynamic (run-time), fault tolerant scheduler targeted to reconfigurable hardware. We present promising preliminary results using the proposed fault-tolerant dynamic scheduler, showing that application performance gracefully degrades when shrinking the available processing resources.
Justin Teller, Füsun Özgüner
IPDPS1
2008 Scheduling reconfiguration at runtime on the TRIPS processor
abstract
We address the problem of scheduling parallel applications onto Heterogeneous Chip Multi-Processors (H- CMPs) containing reconfigurable processing cores. To model reconfiguration, we introduce the novel Mutually Exclusive Processor Groups reconfiguration model, which captures many different modes of reconfiguration. The paper continues by proposing the Heterogeneous Earliest Finish Time with Mutually Exclusive Processor Groups (HEFT- MEG) scheduling heuristic that uses our new reconfiguration model; at compile-time, HEFT-MEG schedules reconfigurations to occur at runtime, with the goal of choosing the most efficient configuration for different application phases. Scheduling reconfiguration to occur at runtime with HEFT-MEG improves the performance of GPS Acquisition, a software radio application, by about 23%, compared to the best single-configuration schedule on the same hardware.
Justin Teller, Fusun Ozgiiner, Robert L. Ewing
IPDPS1