Medical-image processing (MIP) frequently faces challenges related to computational efficiency and memory bandwidth, primarily due to the intensive data movement between processing units and memory. This work explores the emerging paradigm of Processing-in-Memory (PIM) to alleviate these data movement bottlenecks in MIP. It presents the first PIM implementation of five fundamental algorithms widely used in MIP: voxel-counting, thresholding, histogram computation, convolution, and interpolation, outlining specific PIM patterns. The algorithms, implemented using the UPMEM PIM architecture, were evaluated in real non-commercial PIM hardware (20 DDR4-2400 PIM modules providing 160 GB PIM memory), using both synthetic and real data sets of varying image sizes and underlying datatypes (INT8, INT32, FP32), thus covering a wide range of applications. The evaluation results indicate that, for data-intensive tasks, the PIM prototype can improve significantly the computational efficiency over traditional commercial CPU 20 × , and GPU 3 × . This research highlights the potential of PIM for revolutionizing MIP applications by enabling faster and more energy-efficient processing of medical images, thereby addressing critical needs in clinical and research applications.

Processing-using-DRAM (PUD) is a paradigm where the analog operational properties of DRAM are used to perform bulk logic operations.While PUD promises high throughput at low energy and area cost, we uncover three limitations of existing PUD approaches that lead to significant inefficiencies: (i) static data representation, i.e., two's complement with fixed bit-precision, leading to unnecessary computation over useless (i.e., inconsequential) data; (ii) support for only throughput-oriented execution, where the high latency of

Wireless Sensor Networks (WSNs) are widely deployed for real-time monitoring in domains such as industrial automation, smart buildings, and the Internet of Things (IoT). However, continuous sensor data transmission often results in excessive network traffic and elevated energy consumption, particularly in resource-constrained environments. This paper presents a context-aware adaptive data reduction strategy based on the Send-on-Delta (SoD) transmission scheme, enhanced with a dynamic threshold adjustment mechanism driven by Bollinger Bands. A key novelty of the proposed approach lies in its global adaptation strategy: instead of configuring transmission thresholds independently at each node, the system evaluates the collective behaviour of the network to dynamically reconfigure the local thresholds in a coordinated manner. The method is supported by a formal and algorithmic model that captures the network-wide adaptation process, and is validated through a comprehensive evaluation including: a real-world deployment with ESP32-based wireless sensors operating over a 24-hour period; a scalability study with up to 40 simulated nodes derived from real data traces; and a post-hoc comparison against representative SoD variants, such as Send-on-Area and Predictive SoD. Experimental results show that the proposed strategy achieves over 89% reduction in transmission volume while maintaining bounded error, outperforming traditional approaches in lossless, context-sensitive scenarios. These results confirm the method’s effectiveness, robustness, and scalability for energy-efficient communication in WSNs.

The enabling devices and sensors of the Internet of Things (IoT) are characterized by devices with limited resources, where the computation and the energy consumption should be optimized. Application fields such as healthcare or multimedia content bring up security and privacy issues. Therefore, data security is critical. However, to obtain it, high computing resources are required. To avoid it, in this work, we propose a lightweight method to protect data transmissions in sensor devices. We present the GS3 method, it is based on a procedure set by Generating the data block, Shuffling, Scrambling, and applying Substitution boxes on the data. Our experimental results will show that GS3 introduces a minimal overhead, of just two bytes corresponding to the Cyclic Redundant Control 16 (CRC16) integrity control in the length of the messages concerning the original data. According to the execution time with respect of other encryption-based methods, even a 50% less than Chacha20 algorithm, as fewer steps and simpler computation procedures are required. Therefore, GS3 is a good choice to be used in resource-constrained IoT devices in which data integrity and security are required, taking into account the data freshness.

Abstract The use of virtual reality or augmented reality systems in billiards sports are useful tools for pure entertainment or improving the player’s skills. Depending on the purpose of these systems, tracking algorithms based on computer vision must be used. These algorithms are especially useful in systems aiming to reconstruct the trajectories followed by the balls after a strike. However, depending on the billiard modality, the problem of tracking multiple small identical objects, such as balls, is a complex task. In addition, when an amateur or nontop professional player uses low-frame-rate and low-resolution devices, problems such as blurred balls, blurred contours, or fuzzy edges, among others, arise. These effects have a negative impact on ball-tracking accuracy and reconstruction quality. Thus, this work proposes two contributions. The first contribution is a new tracking algorithm called“multiobject local tracking (MOLT)”. This algorithm can track balls with high precision and accuracy even with motion blur caused by low-resolution and low-frame-rate devices. Moreover, the proposed MOLT algorithm is compared with nine tracking methods and four different metrics, outperforming the rest of the methods in the majority of the cases and providing a robust solution. The second contribution is a whole system to track (using the MOLT algorithm) and reconstruct the movements of the balls on a billiard table in a 3D virtual world using computer vision. The proposed system covers all steps from image capture to 3D reconstruction. The 3D reconstruction results have been qualitatively evaluated by different users through a series of questionnaires, obtaining an overall score of 7.6 (out of 10), which indicates that the system is a promising and useful tool for training. Finally, both the MOLT algorithm and the reconstruction system are tested in three billiard modalities: blackball, carom billiards, and snooker.

The Internet of Things (IoT) is usually divided in three layers: Edge, Fog, and Cloud layers. The whole IoT infrastructure deals with large amount of data between layers. Focusing on the Fog layer, the sending/receiving data and further cascade processing of those data in the Fog layer enable the Stream Processing paradigm. Thus, aspects such as the number of connections, delays, buffer size, memory usage, among others, have to be considered to optimize the network traffic. Moreover, these characteristics are affected by uncertainty and imprecision since, for example, the number of connections or the buffer size may be considered low in some cases and high in others. Fuzzy Rule-Based Systems (FRBS) are suitable for addressing complex data and managing their imprecision. The objective of this paper is to propose an approach that optimizes network traffic with the main goal of dynamically and automatically adjusting the queue buffer size in a node to avoid network collapse. The IEEE std 1855-2016 for Fuzzy Markup Language and the open source library JFML are used for their flexibility and interoperability offered by these technologies. The proposal has been simulated in three basic different scenarios involving several network traffic states in a fog infrastructure.

Wireless Sensor Networks (WSN) consist of devices with limited resources to explore and sense the environment in a cooperative way. Security, mainly in terms of guaranteeing the data integrity, is a primary issue for many applications, but with an extra energy cost. Thus, trade-off is required between security level and energy consumption in real applications. First of all, a brief survey about security methods, focusing in data integrity, in WSN is implemented. The objective of this paper is to propose a new data integrity method with medium security levels and low energy cost. Therefore, we propose a new and lightweight mechanism for data integrity with overlapping blocks in WSNs. Hence, an attacker will spend much time and effort to interpret and alter the packets. The experiments were performed using TinyOS 2.1 operating system and TelosB nodes for measuring the overhead in terms of energy consumption, memory, and packet size. Moreover, the receiver is able to detect tampering packets and request those retransmission data. An attacker would require huge amounts of memory and processing time to extract the original information, even for small-sized data blocks. Thus, this fact makes this approach a simple, yet effective, mechanism to protect data whilst enhancing the data integrity.

This paper presents a motion estimation processor based on a dual-core architecture. Both cores are based on bit-serial adder trees. Memory structures are also described. This architecture is bit-precision reconfigurable. Performance results for several smartphones and tablets are presented. Furthermore, hardware results and comparison with other works are included. Real-time processing is achieved for all devices studied.

Current video coding standards, e.g. MPEG-4 H.264/AVC, include Variable Block Size Motion Estimation, in this paper, this process is implemented by a reconfigurable architecture based on Signed Digit arithmetic. Bit serial computation is applied to reconfigure pixel precision. The reconfigurable architectural model is extremely simple to reconfigure. Pixel truncation is used to speed up computation saving up 23.5% of clock cycles for 4-bit precision. This design allows to process all motion vectors of a block in just one iteration. This system has been implemented in FPGA, and HDTVp results are presented. Main characteristics, of this architecture are: very reduced cost, high performance, and reconfigurable pixel precision, these features could be useful in mobile devices.

Computer architecture science evolves continuously. This work describes a methodology to teach a system which is integrated by several processors in just one chip. The description of how to implement a biprocessor system within an FPGA is proposed. Thus, the student will simultaneously acquire advanced knowledge on microprocessors, focusing on the operational behavior and structure of a biprocessor system, which they implement in a real device. Finally, a software layer is provided to execute an application, which proves how the system works. The accomplishment of this practice has been carried out in the first four-month period of 2007 in the 4th year subject “Digital Electronic Systems” of the Engineering Degree in Automatics and Electronics at the University of Córdoba.

Block matching motion estimation takes a great part of the processing time for video encoding. To accelerate this process is must to reach real time video coding. The best motion vector is obtained by full-search block matching algorithm which has to be usually implemented by hardware. In recent years, several FPGA based designs have been proposed since these devices support high number of process elements in parallel mode. In this paper a survey of recent architectures to perform the full-search block matching algorithm in FPGAs is presented. A further comparison on terms of frames per second reached, hardware cost in CLB slices and system frequency is presented