We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC's 0.18 /spl mu/m CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic blocks and switch boxes. Test results demonstrate a throughput of 674 MHz at 1.8 V.

We present an automatic logic synthesis method targeted for high-performance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA. The resulting circuits are inherently pipelined, and can be physically mapped onto our AFPGA with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the FPGA.