Image compression is now essential for applications such as transmission and storage in visual databases. Subband or wavelet transform coding has been proved to be an efficient method of image compression. To exploit the non-stationary nature of image subbands, some image compression techniques have been proposed based on the blockwise classification of image subbands. An advantage of this kind of technique is characterized in a rate-distortion framework in terms of a classification gain. Thus, reaching a maximum classification gain becomes a problem with this kind of technique. To this end, an optimum classification algorithm has been introduced. However, it could not guarantee a maximum classification gain. In this paper, we propose an embedded 1D optimization algorithm to classify blocks of image subbands with a maximum classification gain so as to improve the performance of the blockwise classification image coding.

A novel approach for data transmission in N-ISDN (narrow band integrated services digital network) is proposed. This approach uses the ATM (asynchronous transfer mode) technology normally applied to B-ISDN (broad band ISDN) and provides high performance for the simultaneous transmission of several types of burst information using a single N-ISDN line. It will be compatible to B-ISDN in the future. In the paper, the proposed transmission model is first outlined, including its system description, the layer construction and the functional elements. Then, the transmission protocol is described in detail. Finally, a simulation system is realized, and the performance of the transmission system is confirmed by the simulation results which show the usefulness of the proposed data transmission mode.>

This paper presents the EXMalgorithm, which locates multiple logic design errors in a combinational circuit with multiple output.An error possibility index and a sixvalued simulation method have been introduced to reduce the number of error candidates without missing real errors.Experimental results have shown that this algorithm locates all errors at high hit ratio for benchmark circuits.(3)Indicate error location(s) exactly: what gate(s) or what line(s) are erroneous.(4)Provide detailed solutions for error rectification.Recent researchers have tried to tackle the logic diagnosis problem [2]-[12].However, conventional approaches cannot satisfy above requirements, especially with (1) and (2).In general, logic design errors are embedded in a limited number of locations in the circuit.In order to avoid confusing the designers and to reflect their intention on the circuit, the number of locations changed for error rectification should be as few as possible.Therefore, a logic diagnosis technique should be applicable to line errors as well as gate errors.There are O(nm) possible combinations when considering m errors on n elements.Modeling missing-line errors greatly increases the combinations up to O(n2m) due to the variations in from-to pairs with each line error.Thus, there has been no rectification technique applicable to multiple line errors in a circuit of practical size.

It is pointed out that in the reconfigurable machine (RM) highly flexible architecture combining field-programmable gate arrays (FPGAs) with RAMs supports a wide range of applications. Since its gate-level programmability allows implementation of various kinds of parallel processing techniques, RM provides a performance comparable to that of existing special-purpose engines. A reconfigurable machine prototype (RMP) has been built as the first prototype incorporating five FPGA and four SRAM memory banks. RMP has been applied to logic diagnosis and a logic simulator. The concept of RM may be the best solution to the trade-offs between general-purpose and special-purpose machines. RM will be a hardware platform accelerating a wide range of applications, and also offering an interesting problem in high-level synthesis.>

In this paper, a delayed multipath method for the realization of two-dimensional nonrecursive and recursive digital filters is presented. In this method, a two-dimensional transfer function polynomial is decomposed into a number of shorter transfer function polynomials in parallel. Each of these transfer function polynomials can be realized efficiently in terms of a number of processors. Consequently, high speed computation can be obtained which can be applied to various digital filtering applications. For a two-dimensional finite impulse response digital filter of orders M1 and M2, the maximum throughput can be (M2+1)[(M1+1)/2]2times that of the conventional direct form realization using one processor.

According to the sampling theorem, a faster sampling rate is required in order to process signals containing high frequency components. The processing rate is restricted by the highest operating speed of devices available. This paper presents the design of N-path parallel processing technique which would overcome the speed limitation of present devices. The transfer function of N-path digital filter is shown to be H(zN), where H(z) is the transfer function of each component filter block. This implies that the overall magnitude response of N-path digital filter is a frequency scaled version of that of component filter. In the proposed paper, a scheme to cancel out the unwanted passbands by cascading several N-path filters is first discussed. Then the design procedure of N-path filter from given specification is illustrated using simple example.

The optimum design of recursive digital filters in the cascade realization with respect to the output noise is healed here by taking into account the ordering, the pole-zero pairing, and the selection of configurations of the individual sections. In the first part of this paper, the output noise variances are derived for arbitrary realized cascaded configuration employing either the fixed-point or the floating-point arithmetics. The second part presents a simple algorithm to compute the output noise variance without direct evalution of complex integral. An example is presented in which the individual sections are allowed to take on different configurations.

It is shown that a second-order digital notch filter is uniquely characterized by two distinct parameters, the notch frequency and the 3-dB rejection bandwidth. As a result, such a filter can be realized using only two multipliers. Methods are outlined to design a notch filter for a prescribed notch frequency and a prescribed 3-dB rejection bandwidth, along with procedures for postdesign adjustment of these parameters. All two-multiplier, canonic and noncanonic, notch filter configurations are developed using the multiplier extraction approach. These networks are then compared with regard to the effect of internal multiplication roundoff errors. Results of computer simulation of the notch filter configurations are also included.