Multi-Stage Noise Shaping (MASH) structures have traditionally supported high-resolution analog-to-digital converters (ADCs) by avoiding instability in high-order single loops. While Sturdy MASH (SMASH) reduces the need for precise analog/digital matching in MASH, it reintroduces stability concerns and distortion in integrators due to larger signal swings. This brief presents a modified SMASH design with an efficient architecture that includes one active integrator and three passive ones. Compared to SMASH, the proposed design achieves a flatter signal transfer function (STF) and lower distortion across a wide band. The quantization noise from the first active integrator is filtered by a passive switched-capacitor filter (SCF) before being fed to a second-order passive noise-shaping (NS) quantizer. The structure can be transformed into a cascade of integrators with feedforward (CIFF) delta-sigma modulator (DSM) that traditionally requires a high-gain block. A fourth-order DSM was designed in 65 nm technology for performance validation and comparison, demonstrating an 89.5 dB SNDR and 92.8 dB dynamic range (DR) within a 500 kHz bandwidth using a 25 MHz clock with OSR =25. The simulated modulator power consumption is$290~\mu $W, yielding a Schreier FOM of 181.9 dB.

Pseudo-Pseudo-Differential (PPD) architecture can achieve higher power-efficiency with greatly reduced hardware complexity compared with fully- or pseudo-differential architectures. This paper analyzes the operation of PPD delta-sigma ADC, identifying a delay mismatch between the differential loops, which needs special treatment for stability. Resonator and common-mode feedback implementation is explored. Based on the analysis, a 3rd-order PPD delta-sigma ADC is designed for 16-bit accuracy with 100kHz bandwidth at 9.6MS/s sampling speed.

Mismatch errors in digital-to-analog converters (DACs) can be shaped using various dynamic matching techniques such as data-weighted averaging. However, these techniques become exponentially complex for high-resolution DACs, since they often require conversion from binary coded signals to thermometer coded ones before applying such a scheme. Furthermore, after conversion, it requires N-stage element shuffling circuitry for an N-bit DAC. In this paper, we present a mismatch shaping scheme based on zero mean error encoding technique, which can be applied directly to binary coded signals, without the need for binary to thermometer decoding and element shuffling circuitry.

This article presents a switched-capacitor feedforward technique to enable passive summation in discrete-time (DT) delta-sigma ADCs with only one feedforward capacitor. The proposed technique leads to higher power efficiency and reduced design effort because the amplifier does not carry the input signal thus has a lower output swing, and the power-hungry active adder is avoided. It applies to all kinds of quantizers such as the noise-shaping (NS) SAR, enabling the use of higher order passive NS quantizers for low power applications.

We present a systematic treatment of reciprocity and inter-reciprocity in linear electrical networks, without resorting to the use of Tellegen’s theorem. In Part I, we discuss linear time-invariant networks. In Part II, we expand the applications of our approach to linear periodically time-varying (LPTV) networks.

The second part of this two-part paper addresses reciprocity in linear periodically time-varying (LPTV) networks. We first give a brief overview of LPTV circuits and systems Using this, we derive the adjoint network, which naturally leads to the intriguing concept of time-reversal in the adjoint network. The frequency-reversal and transfer-function theorems are then derived. Finally, we derive some useful properties of LPTV circuits with sampled outputs. The theory is illustrated with examples.

Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) benefit from the energy efficiency of SAR ADCs, and achieve high resolution by oversampling and filtering the residue voltage. Passive NS-SAR ADCs have surpassed their active counterparts in terms of simplicity, low power, and power/voltage/temperature (PVT) robustness. To obtain an aggressive noise transfer function (NTF), however, it requires a large loop gain to compensate for the attenuation due to passive charge sharing. Earlier circuits used a passive gain of 4 to realize a first-order NTF. Higher-order NTF can be achieved with multi-port comparators that provide large active gains at the cost of higher input-referred noise. This paper presents a NS-SAR ADC structure with a passive gain of 4, and a low size-ratioed two-input-pair comparator. It achieves an NTF = (1–0.8z−1)2. Simulations predict that the proposed structure provides higher signal-to-noise ratio than the state-of-the-art ones.

A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13$\mu \text{m}$CMOS technology. It achieved 85.1 dB DR, 82.6 dB SNDR and 90.9 dB SFDR within a 2 kHz signal bandwidth with an oversampling ratio OSR = 32. It consumes 40.8$\mu \text{W}$power using a 1.6 V power supply.

A 0-2 Multi Stage Noise Shaping (MASH) analog-to-digital converter (ADC) is proposed. A SAR ADC and a VCO-based quantizer (VCOQ) are used in the first stage and second stages, respectively. The VCOQ proposed in this paper achieves second-order noise shaping by employing an error feedback architecture. The error feedback architecture is implemented by extracting the quantization noise of the VCOQ as a pulse-width-modulated (PWM) signal, and feeding it back to the VCO input using a charge pump. The proposed architecture filters the charge pump errors. Also, SAR comparator thermal noise requirement is relaxed as the comparator noise is canceled at the output, along with the first stage quantization noise. The proposed ADC was simulated using a 65nm CMOS technology, and an SNDR of 89.5 dB was achieved with an oversampling ratio (OSR) of 20.

In this paper, a novel predictive first-order noise shaping SAR ADC is proposed. Noise-shaping (NS) SAR ADCs have recently gained much attention due to their low power requirements and wide dynamic range. However, for any oversampled ADC, there is a range that each sample will be within guaranteed by input bandwidth. Then SAR ADC operation needs to be performed only around this range. The prediction of range can be done in digital domain which can make better use of process scaling. This saves a significant amount (70%) of power in the A-D conversion. The simulation results show that 109.8 dB SNDR can be achieved with oversampling ratio of 32 while testing only 5 out of 12 bits in each conversion, employing second-order predictor and first order noise shaping.

This short article deals with engineering creativity. In a recent public radio program, creativity was defined as “the ability to generate innovation which works.” For engineering creativity, I would make it more specific: it is the ability to change the direction of technological progress drastically and beneficially, or the ability to induce an inflection point in the development of some engineering field. I shall describe here a few examples of creative ideas that I encountered in my area (analog signal processing and data converters) during my long career in the field. I shall start with some sobering thoughts about the limited range of engineering (indeed, of human) creativity.

Authors write papers; reviewers review them. The relationship between them is a kind of love–hate relationship. Reviewers are loved when they write nice things; they are hated when they niggle. But there is no way the authors could avoid the reviewers. They are an absolute necessity. Without them there would be no quality publishing. This article goes into a little more detail about the interactions between authors and reviewers.

A digital calibration method is presented for delta-sigma ADCs with focus on feedback DAC mismatch error correction. The DAC mismatch information is acquired, and then the nonlinearity is cancelled in the digital domain while the ADC operates. Unlike dynamic element matching which is commonly run between non-overlapping clock phases, the proposed method does not have the restriction and introduces no excess loop delay. The effectiveness of the proposed scheme was demonstrated with implementation of a third-order 15-level delta-sigma ADC.

Integrated sensor interface circuits require power-efficient high-accuracy data converters. In many applications, the best choice is the incremental A/D converters (IADCs) incorporating extended counting. In this paper, we discuss the operation and design of single- and multi-stage IADCs. By using a direct-input feed-forward modulator, the IADC accumulates the residue voltage, and it is easy to implement a hybrid scheme of extended counting. Several hybrid schemes are reviewed and discussed. The energy efficiency c an be improved significantly by re-using the hardware to perform extended counting. A multi-step extended counting scheme is proposed for high-resolution power-efficient conversion. A design example with OSR=320 is described in this paper. By using multi-step extended counting, the SQNR performance is boosted to 108 dB, which is much better than that of a second-order IADC of the same OSR, 94 dB.

In this paper, a micro-power three-step Incremental ADC (IDC) is presented. The proposed IDC achieves an equivalent order of six, realized by only three integrators. Compared to traditional IDCs, the proposed topology can be more power-efficient by implemented with the very low Oversampling Ratio (OSR).

Noise coupling and time interleaving are effective methods for expanding the bandwidth of the low-power wideband delta-sigma modulators. In this paper, a discrete-time ΔΣ modulator topology with these two technologies, combined with shifted loop delays, is proposed. Noise coupling and time interleaving between the two channels enhance the effective order of the noise shaping function. Shifting the loop delays relaxes the critical timing for the DEM. Also, the last integrator in the loop filter performs both integration and active summation. To verify the effectiveness of this topology, a third-order noise-coupled time-interleaved ΔΣ modulator with shifted loop delays is analyzed and simulated.

A new passive switched-capacitor low-pass filter topology is presented. The sampling rate is high due to the reduced number of clock phases and switches connected to each capacitor. Also, this scheme decreases the filter nonlinearity. Verified by simulations, the noise analysis of the filter shows superior performance compared to active SC filters. These features, and a wide frequency tuning range, make the filter suitable for high-speed, low noise, and low power applications. A 7th-order 400 MS/s filter was designed in 0.18 μm AKM CMOS technology. Simulations verify that it can achieve over 100 dB attenuation at 200 MHz frequency, while consuming only dynamic power.

This paper presents a noise-coupled VCO-based two-stage delta-sigma ADC, which achieves third-order noise-shaping with only one active integrator. Noise-coupling technique is applied to VCO-based quantizer to get second-order noise-shaping, used as a second stage in two-stage delta-sigma ADC to overcome the nonlinearity of the VCO. The first stage is a first-order delta-sigma modulator with a three-bit quantizer. To verify the idea, the proposed architecture has been analyzed and simulated.

Presents arguments for the stance that the workforce benefits from colleges and universities that offer engineering students a combination of a quality liberal arts education with the intellectual content of a science/technology/engineering/mathematics (STEM) subjects and courses.

An on-chip teraohm resistance realization scheme using a switched-capacitor ladder is presented in this paper. Linear tuning of the resistance is realized by controlling the sampling frequency. Using this scheme, a band-pass filter with very low corner frequency (~ 0.3 Hz) was implemented in a fully differential amplifier for a small chip area in a standard CMOS process.

A modified low-power switched-capacitor integrator is proposed. It reduces power dissipation without increasing the thermal noise. The proposed integrator is parasitic-insensitive and allows a high linearity. A modified low-distortion self-coupled Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) is proposed to incorporate this new integrator. Analysis and simulations show that the high linearity can be achieved, even with mismatched parasitic capacitors.

A 3rd-order continuous-time ΔΣ modulator with a highly-digital technique for excess loop delay (ELD) compensation is reported. A digitally controlled reference switching matrix is used to replace the commonly used power-hungry signal adder and extra DAC driving the quantizer. The feedback DAC is embedded in the quantizer, and implemented by a few switches. The proposed technique helps the modulator tolerate excess loop delay up to half a clock period. The modulator achieves an SQNR of 83.3 dB in a 15 MHz signal bandwidth. The use of a 2-bit FIR feedback DAC lowers the jitter-induced noise by about 10 dB. The simulated power consumption of the modulator is 7 mW.

Discusses the teaching styles of older professors [age 65 years and older] and their younger counterparts in university education.

A multi-channel mixed-signal noise source with uniform amplitude distribution is presented. Cross-coupled, counter-propagating linear feedback shift registers are used to produce mutually independent binary distributed noises, which in turn generates mutually independent uniformly-distributed discrete-analog noises after digital-to-analog conversion. A stochastic comparator offset cancellation technique based on the proposed analog noise source is demonstrated. Applications include energy-efficient stochastic ADCs and high-density analog built-in self-test.

A two-channel micro-power incremental ADC, designed for biosensor interface circuits, is reported. It uses a noise-coupled multi-bit delta-sigma loop, integrated with a novel digital decimation filter operating in near-threshold. It was realized in the IBM 90 nm CMOS technology. The fabricated 90nm CMOS prototype device, for a 1 Vppdifferential input range, experimentally shows a 74dB SNDR up to 2 kHz (1 kHz/channel) signal bandwidth. The total measured power consumption of the modulator is 13.5 μW.

New foreground digital calibration methods are proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) to reduce the performance loss due to digital-to-analog converter (DAC) mismatch. A set of calibration coefficients which represent the actual weights of the specified patterns is obtained during foreground calibration, and then used during normal operation to correct the SAR ADC output using only a few multiplexers and an accumulator. The simulation results of a 10-bit SAR ADC with the proposed calibration methods show almost 10 effective number of bits (ENOB) with up to 0.5 % binary-weighted DAC mismatch, and more than 12 dB SNDR improvement for even larger DAC mismatch, compared to that without calibration.

A self-calibration technique was developed for SAR analog-to-digital converters that employ binary-weighted capacitors. High-accuracy calibration is achieved by finding and correcting the mismatch of each capacitor independently. The mismatch errors are extracted at power-up, and corrected by individual calibration DACs during the conversion. Unlike in previous schemes, in the proposed method the residual error in the calibration of a capacitor does not affect the calibration of any other capacitor. Simulation results show that the proposed method is also insensitive to the non-idealities of the calibration DACs.

A radix-based digital technique for compensating capacitor mismatch in a two-capacitor DAC is described. Digital input words are pre-distorted with a serial ADC-like algorithm before they are fed into the DAC. The proposed methods provide excellent linearity performance when the DAC is converting a high number of bits. Extra peripheral circuits to achieve the digital compensation are briefly discussed.

New architectures are proposed for the realization of micro-power analog-to-digital data converters. They are based on a time-interleaving and pipelining successive-approximation-register (SAR) structure. The resulting ADCs require very low power dissipation for medium-speed and medium-accuracy data conversion.

The noise-coupling technique is introduced into the design of incremental ΣΔ ADCs using extended counting. A reduced number of integrators and hence lower power dissipation can thus be achieved. To demonstrate the proposed idea, a second-order noise-coupled incremental ΣΔ modulator with extended counting structure was designed and simulated.

In this paper, a general solution is proposed for the excess feedback loop delay issue for a discrete-time ΔΣ ADC. The corresponding low-distortion technique is also illustrated. Finally, the double-sampling ΔΣ ADC immune to the extra loop delay is described and verified through simulation.

A new tuning technique is proposed to enable highly linear active Gm-C filter design. The transconductance cells of the Gm-C filter are tuned using switched resistors (SRs) which change the equivalent reference resistance of each cell. In the master tuning circuit, a feedback loop containing a continuous-time comparator is used to force the equivalent resistance of an SR branch to be equal to that of a switched-capacitor (SC) branch. Thus, using the output of the loop with an automatically adjusted duty cycle, all time constants of the Gm-C filter can be tuned simultaneously. A second-order low-pass Butterworth filter model was developed and simulated. The result verified the effectiveness and excellent linearity of the proposed tuning method.

A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analog-to-digital converters (SAR ADCs). Two junction-split binary-weighted capacitor arrays are used in a coarse/fine quantization scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC.

This paper presents a new zero-optimization scheme for noise-coupled ΔΣ analog-to-digital converters (ADCs). The proposed technique enhances the signal-to-quantization-noise-ratio (SQNR) by optimizing noise-transfer-function (NTF) zero locations to get maximum in-band noise shaping. The amount of SQNR improvement using the new scheme depends on the order of the modulator. Therefore, zero optimization will be used in a first-order and a second-order modified noise-coupled ΔΣ ADCs. The proposed technique enhances the SQNR of the first-order and second-order noise-coupled ΔΣ modulators by 4.5dB and 8.5 dB, respectively.

Architectural considerations for DeltaSigma modulator ADC are critical to achieve wideband and low-power data conversion. A low-distortion single-loop DeltaSigma modulator provides improved performance, and allows robust performance insensitive to circuit errors. However, it requires multiple signal summation at the input of the quantizer, and suffers from reduced signal processing time available for DAC linearization. It is also difficult to incorporate double sampling in the low-distortion modulator. This paper suggests an improved low-distortion modulator topology, derived by signal flow graph manipulations, to overcome these limitations.

This paper presents an enhanced dual-path delta-sigma ADC. The first-order enhancement of the quantization noise shaping is achieved by employing a switched capacitor circuit technique. A test chip, fabricated in a 0.18-µm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75- dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2ndharmonic is −101-dB and the 3rdone is −94-dB when a −4.5-dB 100-kHz input signal is applied.

A digital calibration technique is proposed for DAC mismatches in delta-sigma (ΔΣ) modulators. The delta-sigma modulator works as an incremental ADC in the calibration mode. The DAC mismatches are found by solving linear equations and are compensated digitally. The technique can be used in double-sampling delta-sigma modulators as well.

A novel double-sampling integrator is proposed, which is insensitive to path mismatch, and does not introduce a detrimental extra factor into the loop gain. It allows the use of efficient design methods for ΔΣ ADCs.

Noise-coupled multi-cell delta-sigma ADCs are presented. By providing quantization noise coupling between identical delta-sigma ADCs, one can effectively raise the order of the modulator. Cross-coupled noise injection also provides an efficient way to realize higher-order time-interleaved ADCs.

An enhanced version of Sturdy MASH (SMASH) (Maghari et al., 2006) delta-sigma modulator is proposed. This structure takes advantage of the well-known stability of the MASH structure while greatly reducing its sensitivity to imperfect circuit blocks. Furthermore, no digital noise cancellation filters are needed. Hence there is no matching requirement for the analog and digital paths. With the proposed enhancement in noise shaping, the first and second stage quantization noise experience different (thus mixed) orders of noise shaping, and the accuracy of this modulator is comparable of that of the MASH structure. Simulations results and mathematical analysis demonstrate the effectiveness of this structure.

A novel predictive switched-capacitor amplifier stage is described. It is a track-and-hold amplifier which uses a minimum number of additional capacitors to desensitize the operation to amplifier imperfections. Simulations indicate that the proposed circuit has smaller gain error and lower harmonic distortion than those described in earlier work.

This paper proposes a new dynamic element matching (DEM) technique, segmented date weighted averaging (SeDWA), for application in a multi-bit delta-sigma modulator (DSM). In SeDWA , the DAC elements are divided into several subsets with DWA applied in each set. This allows a simpler and faster implementation, and the selecting sequences for the DAC elements are more randomized than in conventional DWA. This reduces pattern tones, but still provides mismatch error shaping. In the simulated power spectra density (PSD), no in-band pattern tones were observed, and only a moderate rise of the noise floor. Therefore, higher spurious-free dynamic range (SFDR) was achieved. The implementation of SeDWA can be simpler and faster than that of conventional DWA, making it suitable for high-speed applications

A novel track-and-hold amplifier stage is described. It relies on continuous-time correlated double sampling to make the operation insensitive to amplifier imperfections. Simulations indicate that the circuit functions well even if the amplifier gain and bandwidth are low

This paper introduces a new architecture for sensor interface circuits using a delta-sigma modulator. The three-level force feedback allows the use of a digital compensator to stabilize the loop. A 3rd-order delta-sigma structure shapes the opamp noise and allows two-chip implementation with high loop gain at low frequencies.

Cascaded delta-sigma (MASH) converters offer a good compromise between high accuracy, robust stability and speed. However, they are very sensitive to analog circuit imperfections. This paper presents an improved adaptive on-line digital compensation of these errors. Behavioral and circuit-level simulations have confirmed an achievable 13 bit performance and 6 MHz bandwidth for the proposed ADC.

This paper describes a background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analog converter. It can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed.

Novel common-mode feedback circuits are proposed for use in pseudo-differential switched-capacitor circuits. They can be implemented by incorporating just four additional capacitors (and switches) for an integrator, and only two additional capacitors for a residue gain amplifier. The circuits are applicable to very low-voltage switched-capacitor stages realized in submicron low-voltage CMOS processes.

An algorithmic ADC that is insensitive to capacitor mismatch and finite opamp gain and offset is described. Using the differential sampling scheme together with the correlated double sampling (CDS) technique, the virtually error-free and fast multiply-by-two operation is obtained for the proposed ADC. For an N-bit converter, a new output word is obtained every 4N clock periods, and this represents a significant improvement in conversion speed (or efficiency) in comparison to the latest work to achieve the same error compensation. Thus it can be used in applications which require low-cost medium-speed and high-resolution A/D conversion.

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

A high-linearity switched-capacitor (SC) branch using MOSFET capacitors is presented. Simulation results for an SC voltage amplifier show the effectiveness of the branch and its capability to realize linear SC circuits with MOSFET capacitors.

We describe a high-precision calibrating system where the code error voltages of a low-resolution binary-weighted capacitor-array DAC, measured against the precise code voltage references generated by a single-capacitor pulse-counting DAC, are digitized and corrected using a small subbinary-weighted capacitor-array. Computer simulation results are given to demonstrate the operation of the proposed system and the benefits that can be gained by employing gain- and offset-compensated stages.>

As the speed and linearity requirements become harder to meet for analog circuits, it is no longer enough to rely on feedback to enhance linearity. Negative feedback suppresses nonlinearities by a factor equal to the loop gain. This works well at low signal frequencies, but as the signal frequency increases the loop gain drops. Thus, with a limited bandwidth available, nonlinearities should be suppressed at their origin. In this paper, we consider a major source of nonlinearity, namely the input differential pair (IDP) with a cascode current source, commonly used in op-amps. Then a new and simple IDP with a matched channel-length single-device current source is introduced. We show that the modified IDP is more linear and thus creates less harmonics than conventional ones, and that by satisfying a nonrestrictive condition all even harmonics can be eliminated. Experimental results are described which verify the expected reduction of harmonic distortion.>

The usual steps taken to enhance the performance of /spl Sigma//spl Delta/ A/D converters are increasing the order of the loop, or increasing the resolution of the internal quantizer. In this paper, a dual-quantization technique is employed to increase both the order and the resolution of the internal quantizer. Using dual-quantization technique, the sensitivity of the overall resolution to the nonlinearity of the multibit DAC is reduced. The monolithic realization of a third-order 5-bit modulator demonstrated the capabilities of the dual-quantization architecture.>

The FFT algorithms are described which, like those described by Rader and Brenner, use pure real (or imaginary) constant factors. Since these factors contain\cos(2\pik/N)(or\sin(2\pik/N)), these processes are somewhat better conditioned than those of Rader/Brenner, and are comparably efficient.

Symmetry conditions are derived for the amplitude and phase response of vestigial-sideband (VSB) filters. A design technique, based on Szentirmai's frequency transformation, is described for the realization of filters which automatically satisfy these symmetry relations. The synthesis can be carried out with either thesor thez(transformed frequency) variable. It is shown that for sharply selective VSB filters the delay distortion exhibits an even symmetry around the carrier frequency. The equalization of loss and phase distortions can thus be easily carried out in the baseband. A typical design problem is described and solved to illustrate the effectiveness of the suggested synthesis technique.