Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode.

As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon, this paper studies the effect of dynamic IR-drop on the delay of a path. We propose a noise index model, NIM, which can be used to predict the mismatch between expected and real path delays. The noise index considers both the proximity of switching activity to the path and physical characteristics of the design. To evaluate the method, we performed silicon measurements on randomly selected paths from an industrial 65 nm design and compared these with Spice simulations. We show that a very strong correlation exists between the noise index model and the deviations between simulations and silicon measurements.

Power dissipation in digital circuits during scan-based test is generally much higher than that during functional operation. Unfortunately, this increased test power can create hot spots that may damage the silicon, the bonding wires, and even the package. It can also cause intensive erosion of conductors-severely decreasing the reliability of a device. Finally, excessive test power may also result in extra yield loss. To address these issues, this paper first presents a detailed investigation of a benchmark circuit's switching activity during different modes of operation. Specifically, the average number of transitions in the combinational logic of a benchmark circuit during scan shift is found to be approximately 2.5 times more than the average number of transitions during the circuit's normal functional operation. A DFT-based approach for reducing circuit switching activity during scan shift is proposed. Instead of inserting additional logic at the gate level that may introduce additional delay on critical paths, the proposed method modifies the design at the register transfer level (RTL) and uses the synthesis tools to automatically deal with timing analysis and optimization. Our experiments show that significant power reduction can be achieved with very low overhead.

Power consumption during scan-based test becomes a concern in nanometer technologies. Previous test power reduction techniques that insert additional logic in gate-level circuits may result in timing violations. In this paper, we show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic approach proposed previously, we identify power-sensitive scan cells at the prototyping gate level, and we map these cells to their corresponding signal/variable bits at the RT-level. Additional RTL code is added to freeze these power- sensitive bits in order to reduce scan shift power consumption. Experimental results on ITC99 benchmarks show that on average more than 22% power reduction can be achieved when we only freeze the top 1% of power-sensitive bits at RTL. The flow is more practical in terms of timing closure than doing the same at the gate-level.