Demo Data from VLDB 2026 / reviewers in the wild / expert
J. C. DeSouza-Batista
dblp:86/3961
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 91% Hardware accelerators and domain-specific architectures · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › high-level synthesis
data path synthesis |
0.0 | 1 | 1994 | Experience with Image Compression Chip Design using Unified System Construction Tools · DAC 1994 |
Electronic design automation
high-level synthesis |
0.0 | 1 | 1994 | Experience with Image Compression Chip Design using Unified System Construction Tools · DAC 1994 |
Electronic design automation
physical design |
0.0 | 1 | 1994 | Experience with Image Compression Chip Design using Unified System Construction Tools · DAC 1994 |
Hardware accelerators and domain-specific architectures › image processing accelerator
image compression accelerator |
0.0 | 1 | 1994 | Experience with Image Compression Chip Design using Unified System Construction Tools · DAC 1994 |
Methods — techniques the papers use, named apart from their topics
unified system construction tools · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Optimal synthesis of application specific heterogeneous pipelined multiprocessorsabstractWe present a technique and formal model for optimal synthesis of specialized heterogeneous multiprocessors, given task flow graphs to be executed in a pipelined (periodic) fashion. SOS is a formal approach to system synthesis using mixed integer-linear programming, ensuring optimally of the final solutions. SOS was extended to cover the pipelined design style. The extensions were made while trying to avoid a considerable increase in computation time over the non-pipelined case. The extensions include new binary variables as well as new constraints used to ensure numerical convergence. The present tool supports minimization of parameters such as initiation rate, latency and cost.> J. C. DeSouza-Batista, Alice C. Parker |
ASAP | 1 |
| 1994 | Experience with Image Compression Chip Design using Unified System Construction ToolsabstractAbstract { This paper describes the use of Uni ed System Construction tools under development at the University of Southern California. The goal of the project is to automate the construction of heterogeneous, applicationspeci c systems. Key elements of the USC system include multiprocessor synthesis, multi-chip datapath synthesis, memory-intensive synthesis, and multi-chip partitioning. The tools were applied to design of an image compression chip set, and results of using these tools are reported on here. Our results are comparable to manual designs reported in the literature. 1 Pravil Gupta, Chih-Tung Chen, J. C. DeSouza-Batista, Alice C. Parker |
DAC | 3 |