Latency hiding techniques such as multilevel cache hierarchies yield high performance when applications map well onto hierarchy implementations, but performance can suffer drastically when they do not. Identifying and reducing mismatches between an application and the memory hierarchy is difficult without insight into the actual behavior of the hardware implementation. The authors advocate the use of hardware event counters, as a cheap, effective and practical way to tune applications for a given hardware platform. They take a case study approach, focussing on the counters available on the SPARCcenter 2000, a 20 processor, shared-bus based multiprocessor. They describe the tools built to relate hardware event counts to user applications and give examples to illustrate how these tools are useful in practice. They conclude with a critique of the current hardware counters, offering a user's perspective on how they could be redesigned to be more effective.>

The authors describe Mtool, a software tool for analyzing performance losses in shared memory parallel programs. Mtool augments a program with low overhead instrumentation which perturbs the program's execution as little as possible while generating enough information to isolate memory and synchronization bottlenecks. After running the instrumented version of the parallel program, the programmer can use Mtool's window-based user interface to view compute time, memory, and synchronization objects. The authors describe Mtool's low overhead instrumentation methods, memory bottleneck detection technique, and attention focusing mechanisms, contrast Mtool with other approaches, and offer a case study to demonstrate its effectiveness.>

Article Free Access Share on Performance debugging shared memory multiprocessor programs with MTOOL Authors: Aaron J. Goldberg Department of Computer Science, Stanford University Department of Computer Science, Stanford UniversityView Profile , John L. Hennessy Computer Systems Laboratory, Stanford University Computer Systems Laboratory, Stanford UniversityView Profile Authors Info & Claims Supercomputing '91: Proceedings of the 1991 ACM/IEEE conference on SupercomputingAugust 1991 Pages 481–490https://doi.org/10.1145/125826.126075Online:01 August 1991Publication History 31citation529DownloadsMetricsTotal Citations31Total Downloads529Last 12 Months7Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper presents a new, relatively inexpensive method for detecting regions (e.g. loops and procedures) in a program where the memory hierarchy is performing poorly. By observing where actual measured execution time differs from the time predicted given a perfect memory system, we can isolate memory bottlenecks. MTOOL, an implementation of the approach aimed at applications programs running on MIPS-chip based workstations is described and results for some of the Perfect Club and SPEC benchmarks are summarized.

A robust and low cost realtime pitch extractor is presented in this paper. The algorithm uses long-term prediction with two prediction coefficients calculated from the autocorrelation function (ACF) of LPC residual error signal. This pitch extractor has worked successfully in a narrow band realtime LPC vocoder operating in highly noisy environments, where a conventional AMDF (Average Magnitude Difference Function) pitch extractor failed to provide satisfactory results. The algorithm requires some extra arithmetic operations in addition to the ACF calculations of LPC residual error signals. But, it is implemented in realtime with the programmable microcomputer chip NEC uPD7720. This chip can multiply and accumulate in parallel with the ALU operation during a single machine cycle allowing pitch detection with multiplies.

This paper will describe the design of a robust 9.6 kb/s speech transmission system which degrades slowly under high error rate conditions. The system is based upon a combination of adaptive transform coding (ATC) principles and a vocoder-driven strategy (VDS) proposed by previous authors and operates in real-time on a commercially available array processor (1), (3). The channel error protection process utilizes a fixed block length BCH code on a rank ordered message list composed of discrete cosine transform (DCT) coefficients and side band information. The resultant system exhibits little degradation at 1 percent channel error rates and is not degraded perceptually by inaccurate pitch estimation.

This paper describes a voice digitizer whose 16,000 bps data rate contains an embedded 2400 bps linear predictive coder. This 2400/16,000 bps multirate coder eliminates the need for tandeming conversion when going from 2400 bps to 16,000 bps systems and when going from 16,000-bps to 2400-bps systems. Because the 16,000 bps rate uses the principles of adaptive predictive coding, this multirate processor eliminates sensitivites to pitch and voicing inaccuracies at the 16,000 bps rate. Applications include a single-voice processor for narrowband and wideband communication systems and a single-voice digitization system for packetized voice systems requiring multirate algorithms that optimize network loading.

In this paper, we discuss how adaptive predictive coders employing pitch and coefficient predictors perform when combined with adaptive multilevel quantizers to transmit speech at 16 Kb/s. Performance curves based on fixed point simulations provide a quantitative signal-to-noise analysis as a function of predictor complexity, quantizer adaptation strategy and channel error rate. For example, a fourth order adaptive predictor with pitch loop and adaptive 8-level quantization provides reconstructed speech that is perceptually indistinguishable from the original 2500 Hz band limited input. With channel errors, performance is found to be both a sensitive function of quantizer adaption strategy and predictor complexity. While complex predictors are superior to CVSD at error rates below 10-4, CVSD degrades less rapidly as channel errors increase, At 10-2BER and above, CVSD outperforms the other techniques studied.

In this correspondence the "well known" necessary and sufficient stability conditions for a recursive filter are derived, and a new gradient algorithm is presented that guarantees the stability of a recursive filter. Recent interest in recursive filters is given in [1]-[5].

This paper describes a real-time computer implementaation of a fourth-order adaptive predictive coder (APC) which transmits speech at 6400 bits/s. To reduce the demands on the central processor, the terminal uses the average magnitude difference function (AMDF) for pitch extraction and calculates the predictor coefficients and reflection coefficients assuming stationarity of the input data. With 16-bit fixed-point arithmetic processing, the coder achieves an intelligibility score of 87 percent on the diagnostic rhyme tests (DRT) and produces speech with acceptable voice naturalness even in the presence of acoustic background noise.