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Daryl Odnert

dblp:86/5376 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1990
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
code generation		 0.011990
Register Allocation Across Procedure and Module Boundaries · PLDI 1990
Compilers and program optimization › register allocation
interprocedural register allocation		 0.011990
Register Allocation Across Procedure and Module Boundaries · PLDI 1990
Compilers and program optimization
register allocation		 0.011990
Register Allocation Across Procedure and Module Boundaries · PLDI 1990
Processor architecture and microarchitecture › instruction set architecture › RISC
RISC processor		 0.011990
Register Allocation Across Procedure and Module Boundaries · PLDI 1990

Methods — techniques the papers use, named apart from their topics

interprocedural analysis · 0.0global variable promotion · 0.0
YearPublicationVenuePosition
1990 Register Allocation Across Procedure and Module Boundaries
abstract
This paper describes a method for compiling programs using interprocedural register allocation. A strategy for handling programs built from multiple modules is presented, as well as algorithms for global variable promotion and register spill code motion. These algorithms attempt to address some of the shortcomings of previous interprocedural register allocation strategies. Results are given for an implementation on a single register file RISC-based architecture.
Vatsa Santhanam, Daryl Odnert
 PLDI2