A special computer for high-precision arithmetic features an ALU that is dynamically reconfigurable under program control. The 256-bit ALU consists of 8 32-Mt slices each of which has its own ALU operation code in each microinstruction. The slices can remain logically separated from each other, or he dynamically connected to either or both of their neighbors under control of a segment control code that is part of each microinstruction. The micro-assembly language designed for the machine includes special features to assist in the control of the segmentation, data addressing, and control sequencing. Estimations of the times required to execute arithmetic operations on the machine show that it will be exceptionally fast for problems in computational number theory and factoring of integers.

Factoring, primality testing, and other problems of current interest [1, 2, 3, 4, 5, for example] in experimental number theory require machines with different architectures from those for any other application. Algorithms for such problems are small, but their execution requires high-speed arithmetic on very long integers interspersed with shorter precision computing that can conveniently be done by several processors acting in parallel. In this paper, we describe the preliminary design of a processor specifically for computational number theoretic problems. The primary component is a 256-bit ALU which is dynamically reconfigurable to provide for parallel independent operations on groups of 32-bit subwords within the 256-bit word.