The future of microelectronics will be determined largely by the success of the semiconductor industry in continuing to exploit the "productivity engine". The cycle of this engine is: 1) exponential trends in technology and productivity improvement, which enable 2) expanding markets and revenues, which enable 3) larger research and development (R&D) and manufacturing investments, which, in turn, enable 1). This paradigm has served us well for almost four decades, and the semiconductor industry is probably unique in maintaining such a steep performance/price improvement trend for its products over such a relatively long period. Agriculture has shown improvement over a longer period (thousands of years) but at a much slower pace. Other industries have enjoyed occasional step-function advances, but not on a regular basis spanning several decades. Of course, there is a diversity of opinion about how much longer the fundamental trends (e.g., "Moore's law") can persist. In this paper, we will discuss some of the challenges and opportunities associated with the extension of these trends and indulge in some speculation about potential future scenarios in microelectronics business and technology.

The benefits of gigabit chips, which will enter production around the year 2000, are discussed. These chips will be enablers for smart and brilliant systems. The systems will be ultralow power. The design and software productivity enhancements needed are described. The numerous manufacturing challenges that lie ahead in the 1990s represent opportunities to implement advanced concepts currently under development in the industry. It is predicted that software-driven concepts such as flexible manufacturing and distributed computer integrated manufacturing will evolve. Processing concepts using cluster tools, real-time process control, all-dry processing, and wafer microenvironments should be ready for manufacturing in the gigabit age. The costs of electronics should continue to decrease, concomitant with extraordinary increases in functionality and performance.>

An integrated and efficient approach is developed for automated statistical circuit design. One major problem in statistical circuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device parameters. A statistical model for MOS VLSI circuits has been developed in which only the interdie variations are considered, since they are much larger than the local intradie variations. Therefore, the set of statistical variables are different from the set of design parameters, and this leads to a resolution of the problem of dimensionality associated with statistical design. In this statistical model, variations in device length and width, oxide capacitance, and flat band voltage, have been shown to be the principal process factors responsible for the statistical variation of device characteristics. A scalable MOS model has been developed to represent changes in the device model parameters as functions of these principal factors. This accurate and simple statistical modeling approach uses only four statistical variables, and thus permits computationally efficient statistical parametric yield estimation (SPYE). The direct approach for transient sensitivity computation has been implemented in SPICE to allow very efficient computation of performance function sensitivities. An efficient technique for computing the yield gradient using the SPYE and transient sensitivity results is discussed and an example is presented to demonstrate its use in parametric yield optimization.

VLSI circuit simulation requires computationally efficient MOSFET models. In this paper, VLSI circuit simulator models for the active device and some important passive devices are described. A quasi-physical short channel MOSFET current model is derived. This current model contains both above-threshold and subthreshold components. The values of the model parameter are extracted automatically from measured I-V data. The reduction in process information in this representation is shown to be tolerable using a proper quantization of the geometry and device type space. Narrow width effect is also included. A charge conserving MOSFET capacitor model is also given. The importance of the parasitic devices on VLSI circuit is shown and a model for the fringing capacitance due to finite gate thickness is introduced. A "process box" based on the statistical variation of parameters is extracted from a completely automated device characterization system. Experimental results indicate that the width and length are independent random variables. This statistical information allows the circuit response to be simulated across the process window.