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S. R. Ahuja

dblp:86/6548 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1981
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Interconnection networks and networks-on-chip · 68% Memory systems · 18% Parallel and multicore computing · 9%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › bus-based interconnection
bus architecture		 0.011981
Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems · ISCA 1981
Interconnection networks and networks-on-chip › bus-based interconnection
high-speed bus		 0.011981
Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems · ISCA 1981
Memory systems › memory architecture
parallel memory organization		 0.011977
A Modular Memory Scheme for Array Processing · ISCA 1977
Parallel and multicore computing › parallel computing
multiprocessing		 0.011981
Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems · ISCA 1981
Interconnection networks and networks-on-chip › switching network › multistage interconnection network
perfect shuffle		 0.011977
A Modular Memory Scheme for Array Processing · ISCA 1977

Methods — techniques the papers use, named apart from their topics

performance analysis · 0.0
YearPublicationVenuePosition
1981 Performance Analysis of High-Speed Digital Buses for Multiprocessing Systems
William L. Bain, S. R. Ahuja
 ISCA2
1977 A Modular Memory Scheme for Array Processing
abstract
This paper presents a parallel memory scheme suited for pipelined processing units. The scheme is shown to be modular, relatively low cost and flexible. The scheme allows an arbitrary number of variables in the vector operations. It is shown that data alignment is handled by a simple interconnection scheme and that the interconnection scheme can be implemented in the memory modules. It is shown that the scheme facilitates efficient implementation of the Perfect Shuffle interconnection, hence the implementation of parallel algorithms using that interconnection scheme.
S. R. Ahuja, J. Robert Jump
 ISCA1