A slew-driven clock tree synthesis (SLECTS) methodology is proposed for nanoscale technologies where the interconnect resistance dominates device resistance, thereby increasing the challenge of satisfying the slew constraint. This issue is exacerbated at lower voltages due to degraded drive ability of the clock buffers. A paradigm shift from the traditional delay (and skew)-driven approaches to the proposed slew-driven methodology is therefore required. SLECTS is developed in this paper to satisfy tight slew constraints, which can be costly or infeasible with delay (skew)-driven methodologies and reduce the power dissipation of the clock tree, since the slew and skew constraints are simultaneously and methodically considered. Experimental results performed on an industrial circuit with more than 1M gates designed in 28-nm technology demonstrate that clock power is reduced by approximately 15% as compared to a commercial clock tree synthesis tool under similar slew and skew constraints.

Power gating is a widely used leakage power saving strategy in modern chip designs. However, power gating introduces unique power integrity issues and trade-offs between switching and rush current (wake-up) supply noises. At the same time, the amount of power saving intrinsically trades off with power integrity. In addition, these trade-offs significantly vary with supply voltage. In this article, we propose systemic decoupling capacitors (decaps) optimization strategies that optimally trade-off between power integrity and leakage saving. Specially, new global decap and reroutable decap design concepts are proposed to relax the tight interaction between power integrity and leakage saving of power gated PDNs with a single supply voltage level. Furthermore, we propose a flexible decap allocation technique to deal with the design trade-offs under multiple supply voltage levels. The proposed strategies are implemented in an automatic design flow for choosing the optimal amount of local decaps, global decaps and reroutable decaps. The conducted experiments demonstrate that leakage saving can be increased significantly compared with the conventional PDN design approach with a single supply voltage level using the proposed techniques without jeopardizing power integrity. For PDN designs operating at two supply voltage levels, the optimal performance is achieved at each voltage level.

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. In this paper we propose a comprehensive sensitivity metric which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations. We develop first-order models to compute these sensitivities, and perform robust layout optimization by minimizing the total delay sensitivity to reduce the delay variation on the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners to reduce the leakage current on the process corner. The results on industrial 45nm node standard cells show up to 76% improvement in non-rectangular delay variation under nominal process condition, 24% reduction in the delay difference between the fastest and slowest process corners, and up to 90% reduction in leakage current at the fastest process corner.

SSTA has received a considerable amount of attention in recent years. However, it is a general rule that any approach can only be as accurate as the underlying models. Thus, variation models are an important research topic, in addition to the development of statistical timing tools. These models attempt to predict fluctuations in parameters like doping concentration, critical dimension (CD), and ILD thickness, as well as their spatial correlations. Modeling CD variation is a difficult problem because it contains a systematic component that is context dependent as well as a probabilistic component that is caused by exposure and defocus variation. Since these variations are dependent on topology, modern-day designs can potentially contain thousands of unique CD distributions. To capture all of the individual CD distributions within statistical timing, a transistor-specific model is required. However, statistical CD models used in industry today do not distinguish between transistors contained within different standard cell types (at the same location in a die), nor do they distinguish between transistors contained within the same standard cell. In this work we verify that the current methodology is error-prone using a 90 nm industrial library and lithography recipe (with industrial OPC) and propose a new SSTA delay model that on average reduces error of standard deviation from 11.8% to 4.1% when the total variation (sigma/mu) is 4.9% - a 2.9X reduction. Our model is compatible with existing SSTA techniques and can easily incorporate other sources of variation such as random dopant fluctuation and line-edge roughness.

Decap allocation are the primary methods for addressing the dynamic voltage noise problem of on-chip power networks. When space in the immediate proximity of a hot spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation we proposed an effecient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10]. Experimental results on two actual chip designs demonstrate the area and run-time efficiency of the co-optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible solution.

We propose a novel and efficient incremental analysis technique for 'what-if analysis of on-chip power distribution networks (PDN). Effect of local modifications to a PDN, including local topology changes, can be quickly analyzed without need for very expensive re-analysis of the entire modified network. We borrow ideas from a fictitious domain method that has been successfully used in solving partial differential equations arising from inhomogeneous problems in mechanics. The effect of local wiring modifications in several PDN regions is mimicked by applying fictitious currents at the boundaries of these regions in the original unmodified network. The fictitious currents are calculated from component sub-problems in a low-computation iterative procedure. The practicality of this method for use in what-if analysis is demonstrated with several large power networks from actual industrial designs. It analyzes a modified network with few million changes in a fraction of time it would take for a complete re-analysis.

As technology scales, it is becoming increasingly difficult for simulation and timing models to accurately predict silicon timing behavior. When a collection of chips fail in timing in a similar way, diagnosis and silicon debug look to find the root-causes for the failure. However, little work has been done to develop a methodology that looks for useful design information in the good-chip data. This paper describes a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We explain how to utilize this methodology for evaluating the risk of timing modeling.

We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macromodeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and through certain approximations. To reduce the error caused by linearization, we do multiple iterations of the linear program. Experimental results demonstrate that, with the proposed algorithm, even very large power networks (eg. 5 million nodes) can be optimized in a couple of hours with 1-2 transient analyses. Comparison of our algorithm with another heuristic method shows area efficiency and run time advantage of our method.

Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at the best vantage locations helps to reduce the number of supply connections necessary for obtaining quality power distribution. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power-supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins, and regulators. The problem is modeled as a mixed-integer linear program (MILP) with the help of macromodeling techniques. Two new heuristics, in addition to the commonly used branch-and-bound technique, are proposed to make the problem tractable. The effectiveness of the proposed technique is demonstrated on several real chips and memories used in low-power and high-performance applications.

Power supply integrity analysis is critical in modern high perfor-mance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical information is extracted, including correlation infor-mation between blocks in both space and time. We then propose a method to propagate the statistical parameters of the block currents through the linear model of the power grid to obtain the mean and standard deviation of the voltage drops at any node in the grid. We show that the run time is linear with the length of the current wave-forms allowing for extensive vectors, up to millions of cycles, to be analyzed. We implemented the approach on a number of grids, including a grid from an industrial microprocessor and demonstrate its accuracy and efficiency. The proposed statistical analysis can be use to determine which portions of the grid are most likely to fail as well as to provide information for other analyses, such as statistical timing analysis.

Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins and regulators. The problem is modeled as a mixed integer linear program using macromodeling techniques and several heuristic techniques are proposed to make the problem tractable. The effectiveness of the proposed techniques is demonstrated on several real chips and memories used in low-power and high-performance applications.

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intra-die variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter- and intra-die variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.

Static timing analysis has traditionally used the PERT method for identifying the critical path of a circuit. The authors show in this paper that due to the influence of the transition time of a signal on the subsequent path delay, the traditional timing analysis approach can report an optimistic circuit delay and may identify the wrong critical path. Also, the calculated circuit delay is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. The authors also examine an alternate approach where the propagated signal is constructed by combining the latest arrival time and the slowest transition time from all signals incident on a node. While this approach remedies the problem of discontinuity, it can significantly overestimate the circuit delay and can also identify the wrong critical path. In this paper, they therefore propose a new timing analysis algorithm and prove that it computes the correct and continuous timing graph delay and the proper critical path. The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. They show that the algorithm propagates the sufficient and necessary set of signals for computing the delay of a general timing graph. The authors also introduce a new property of digital gates, referred to as the transition shift property, and, using this property, show that the number of propagated signals can be significantly reduced for timing graphs of digital circuits. Finally, they discuss the computation of required times and node slacks for the traditional approaches and propose corresponding algorithms for the new approaches. They show that while the traditional approach can incur both a positive or negative error in the computed slack, the proposed algorithms compute a conservative slack for off-critical nodes and the correct and continuous slack for the critical path. The proposed algorithms were implemented in an industrial static timing analysis and optimization tool, and the authors present results for a number of industrial circuits. Their results show that the traditional timing analysis method underestimates the circuit delay by as much as 39%, while the discussed alternate approach can overestimate circuit delay by as much as 17%. The proposed method computes the correct delay, while incurring only a small run time overhead in all cases.

Article Share on On the interaction of power distribution network with substrate Authors: Rajendran Panda Motorola, Inc., Austin, TX Motorola, Inc., Austin, TXView Profile , Savithri Sundareswaran Motorola, Inc., Austin, TX Motorola, Inc., Austin, TXView Profile , David Blaauw Motorola, Inc., Austin, TX Motorola, Inc., Austin, TXView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001Pages 388–393https://doi.org/10.1145/383082.383188Published:06 August 2001Publication History 12citation288DownloadsMetricsTotal Citations12Total Downloads288Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional method for timing analysis may identify the incorrect critical path and report an optimistic delay for the circuit. We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. We propose a new timing analysis algorithm which resolves both these issues. The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. The algorithm for propagating the corresponding required times is also presented. We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional timing analysis method may not. We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes. In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy. Finally, we show how the proposed algorithm was efficiently implemented in an industrial static timing analysis and optimization tool, and present results for a number of industrial circuits. Our results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time.