Growing complexity in system-on-a-chip (SoC) design demands effective approaches to explore various architectures quickly for the target applications. With the common use of intellectual properties (IPs) in SoC and the large amount of data interchanges among IPs, communication architecture significantly affects the system in terms of power and performance. Therefore, designers should carefully plan the communication architecture to meet the power and performance requirements. While repeatedly performing a power optimization under a performance constraint approach N times seems practical for the power and performance co-exploration, the time required to explore such solutions inevitably increases, since there are numerous performance constraints. This paper presents a pseudo-parallel method for bus architecture exploration at the system level (PBAES) to speedup the power and performance of co-exploration time. PBAES can intelligently search interesting portions of the design space to enhance the efficiency of co-exploration, and share the candidate solutions of each to achieve a more rapid overall exploration. The experimental results indicate that PBAES is 1.6 times to 14 times faster than an approach without the pseudo-parallel method with a generated architecture of similar quality.