VLDB 2026 Research / reviewers in the wild / expert
Jae-Woong Chung
dblp:86/8290
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 54% Parallel and multicore computing · 46% | |
| Software engineering, system software, and programming languages
1 paper |
Concurrent programming · 87% Compilers and program optimization · 13% |
Topics — the 10 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming › transactional memory
hardware transactional memory |
0.1 | 1 | 2010 | Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack · EuroSys 2010 |
Concurrent programming
transactional memory |
0.1 | 1 | 2010 | Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack · EuroSys 2010 |
Parallel and multicore computing › transactional memory
hardware transactional memory |
0.1 | 1 | 2010 | ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory · MICRO 2010 |
Processor architecture and microarchitecture
instruction set architecture |
0.1 | 1 | 2010 | ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory · MICRO 2010 |
Processor architecture and microarchitecture › instruction set architecture
instruction set extension |
0.1 | 1 | 2010 | Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack · EuroSys 2010 |
Processor architecture and microarchitecture
speculative execution |
0.1 | 1 | 2010 | ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory · MICRO 2010 |
Parallel and multicore computing
transactional memory |
0.1 | 1 | 2010 | ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory · MICRO 2010 |
Compilers and program optimization › compiler construction
compiler support for transactional memory |
0.0 | 1 | 2010 | Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack · EuroSys 2010 |
Parallel and multicore computing › concurrent data structures
lock-free data structures |
0.0 | 1 | 2010 | ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory · MICRO 2010 |
Parallel and multicore computing
synchronization |
0.0 | 1 | 2010 | ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory · MICRO 2010 |
Methods — techniques the papers use, named apart from their topics
software fallback · 0.2cycle-accurate simulation · 0.2compiler extension · 0.2out-of-order simulation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | Evaluation of AMD's advanced synchronization facility within a complete transactional memory stackabstractAMD's Advanced Synchronization Facility (ASF) is an x86 instruction set extension proposal intended to simplify and speed up the synchronization of concurrent programs. In this paper, we report our experiences using ASF for implementing transactional memory. We have extended a C/C++ compiler to support language-level transactions and generate code that takes advantage of ASF. We use a software fallback mechanism for transactions that cannot be committed within ASF (e.g., because of hardware capacity limitations). Our evaluation uses a cycle-accurate x86 simulator that we have extended with ASF support. Building a complete ASF-based software stack allows us to evaluate the performance gains that a user-level program can obtain from ASF. Our measurements on a wide range of benchmarks indicate that the overheads traditionally associated with software transactional memories can be significantly reduced with the help of ASF. David Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, Etienne Rivière |
EuroSys | 2 |
| 2010 | ASF: AMD64 Extension for Lock-Free Data Structures and Transactional MemoryabstractAdvanced Synchronization Facility (ASF) is an AMD64 hardware extension for lock-free data structures and transactional memory. It provides a speculative region that atomically executes speculative accesses in the region. Five new instructions are added to demarcate the region, use speculative accesses selectively, and control the speculative hardware context. Programmers can use speculative regions to build flexible multi-word atomic primitives with no additional software support by relying on the minimum guarantee of available ASF hardware resources for lock-free programming. Transactional programs with high-level TM language constructs can either be compiled directly to the ASF code or be linked to software TM systems that use ASF to accelerate transactional execution. In this paper we develop an out-of-order hardware design to implement ASF on a future AMD processor and evaluate it with an in-house simulator. The experimental results show that the combined use of the L1 cache and the LS unit is very helpful for the performance robustness of ASF-based lock free data structures, and that the selective use of speculative accesses enables transactional programs to scale with limited ASF hardware resources. Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman |
MICRO | 1 |