Split capacitor digital-to-analog converters (split-CDACs) are a promising method to reduce area but face challenges with parasitic sensitivity in high-resolution settings for successive approximation register analog-to-digital converters (SAR ADCs) design. This article introduces a split-CDAC design for improving area efficiency for higher bit resolution by reducing parasitic sensitivity and mismatch. A fundamental reason for the increased parasitic sensitivity stems from the fractional sizing of the bridge capacitor and a small redundant capacitor at the split node. The proposed split-CDAC uses a unit capacitor-based bridge capacitor and a proportionally scaled large redundant unit capacitor, which minimizes these effects to a large extent while achieving linearity. It achieves six times better parasitic sensitivity than a conventional split-CDAC by using six-unit capacitors as a bridge capacitor and 12 times better area efficiency than the conventional binary-weighted CDAC. The proposed fully common-centroided and shielded unit capacitor array, implemented in a 65 nm CMOS process, effectively reduces parasitic and mismatch sensitivity using a simple layout structure. The implementation achieves an INL of less than 1.2 LSB, measured across 21 chips, without mismatch calibration and opens new possibilities for high-precision applications across diverse domains.

In this letter, we have implemented and compared two neural coding algorithms in the networks of spiking neurons: Winner-takes-all (WTA) and winners-share-all (WSA). Winners-Share-All exploits the code space provided by the temporal code by training a different combination of [Formula: see text] out of [Formula: see text] neurons to fire together in response to different patterns, while WTA uses a one-hot-coding to respond to distinguished patterns. Using WSA, the maximum value of [Formula: see text] in order to maximize information capacity using [Formula: see text] output neurons was theoretically determined and utilized. A small proof-of-concept classification problem was applied to a spiking neural network using both algorithms to classify 14 letters of English alphabet with an image size of 15 [Formula: see text] 15 pixels. For both schemes, a modified spike-timing-dependent-plasticity (STDP) learning rule has been used to train the spiking neurons in an unsupervised fashion. The performance and the number of neurons required to perform this computation are compared between the two algorithms. We show that by tolerating a small drop in performance accuracy (84% in WSA versus 91% in WTA), we are able to reduce the number of output neurons by more than a factor of two. We show how the reduction in the number of neurons will increase as the number of patterns increases. The reduction in the number of output neurons would then proportionally reduce the number of training parameters, which requires less memory and hence speeds up the computation, and in the case of neuromorphic implementation on silicon, would take up much less area.

A synthesizer design for achieving high frequency resolution and stability is described. Fractional-N resolution is achieved, without using the classical dual-modulus divider, by exploiting the predictable phase evolution. The predicted phase is added in the feed-forward path within an integer-N analog PLL. A digital pulse generator (DPG) cancels the expected phase difference between the reference and feedback signal. A high-speed current-steering DAC increases the effective pulse width resolution overcoming the limit imposed by the VCO frequency. A novel ping-pong swallow counter topology masks the pipeline delay of a synchronous frequency divider used in the DPG. The architecture has been designed and simulated in a CMOS 0.13 μm technology. For a 5 GHz VCO and 100 MHz reference, the synthesizer exhibits 1.5 Hz frequency steps with the wide-band performance of a conventional charge pump PLL.

Memristors are emerging as powerful nanoscale devices for diverse applications, such as high-density memories and neuromorphic applications. However, this nascent technology requires considerable advancement before this vision is realized. We present a highly configurable CMOS interface chip which enables the characterization of on-chip memristors, especially for memory applications. The chip was fabricated in On-Semi 3M2P 0.5 μm occupying 2×2 mm2. The chip design allows for post-CMOS fabrication of memristors. The interface between the memristor and the CMOS circuitry was provided via a top metal contact. The chip was designed to support an area-distributed interface decoupling CMOS pitch and memristor pitch, enabling high-density memristor integration. Measurement results on post-CMOS fabricated Ag/SiO2/Pt memristive devices are reported. Though we have shown the results from one memristive material stack, thorough chip characterization demonstrates the versatility of the chip enabling its use with a wide variety of materials stacks.

Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy. We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7×--11× average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.

Local thermal hot-spots in microprocessors lead to worst-case provisioning of global cooling resources, especially in large-scale systems where cooling power can be 50~100% of IT power. Further, the efficiency of cooling solutions degrade non-linearly with supply temperature. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots. Applying current to a superlattice TEC-film that is deposited between silicon and the heat spreader results in a Peltier effect, which spreads the heat and lowers the temperature of the hot-spot significantly and improves chip reliability. In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power.