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H. Alla

dblp:87/121 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
1 paper
Automated reasoning and model checking · 50% Automata and formal languages · 50%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Automated reasoning and model checking
discrete event systems
0.011998
On the Synthesis of a Controllable Supervisor for Discrete Processes Modeled by Temporal Petri Nets · ICRA 1998
Automata and formal languages
petri nets
0.011998
On the Synthesis of a Controllable Supervisor for Discrete Processes Modeled by Temporal Petri Nets · ICRA 1998
Automated reasoning and model checking › discrete event systems
supervisory control
0.011998
On the Synthesis of a Controllable Supervisor for Discrete Processes Modeled by Temporal Petri Nets · ICRA 1998
Automata and formal languages › petri nets
temporal petri nets
0.011998
On the Synthesis of a Controllable Supervisor for Discrete Processes Modeled by Temporal Petri Nets · ICRA 1998
Embedded and real-time systems › manufacturing systems
flexible manufacturing systems
0.011998
On the Synthesis of a Controllable Supervisor for Discrete Processes Modeled by Temporal Petri Nets · ICRA 1998

Methods — techniques the papers use, named apart from their topics

petri net synthesis · 0.0
YearPublicationVenuePosition
1998 On the Synthesis of a Controllable Supervisor for Discrete Processes Modeled by Temporal Petri Nets
abstract
The paper presents the conceptual framework and the synthesis procedure for temporal discrete event system supervisor. The approach is suitable in controlling systems as flexible manufacturing systems, in which certain durations of operations are not precisely known a priori. In this way, the model embodies temporal uncertainties of the process and the supervisor is "robust" to this indeterminism. The synthesis procedure could result in one ore more controllable supervision policies.
Simona Caramihai, H. Alla
ICRA2