Abstract Subnet-based wireless network-on-chip (WNoC) architecture often experiences inefficient core utilization, leading to localized overheating and performance loss. This study introduces a hop-based approach that selects cores for wireless router assignment without forming subnets and schedules jobs with fairness by assigning tasks to the coolest cores. This approach aims to maintain balanced heat distribution across WNoC cores while improving performance. Wireless router cores are chosen so that the maximum hop count from any core to the nearest wireless router remains fixed. Jobs are scheduled using an improved shortest remaining job first (SRJF) algorithm for fairness, and cores are selected based on their lowest Heat Indicator (HI) values. We simulate 49-, 81-, and 144-core WNoC in 1-hop, 2-hop, and 3-hop configurations using benchmark-inspired 184 jobs. Simulation results show that the 2-hop WNoC achieves fair heat distribution and provides a balanced performance across the evaluated metrics, reducing the number of wireless routers compared to hop-1 and lowering latency and power consumption compared to existing subnet-based WNoC systems.

Abstract Computer-aided diagnosis (CADx) systems often involve error-prone and/or manual processes. Recent studies show that various machine learning models have the potential to improve the accuracy of CADx systems. However, existing models suffer from low prediction accuracy. In this work, we present research findings to improve the effectiveness of CADx systems for detecting skin diseases by adopting optimized ensemble machine learning models. The investigation encompasses the exploration of three popular classification methods: linear discriminant analysis (LDA), support vector machine (SVM), and convolutional neural network (CNN); two customized CNN models: LeNet-5 and ResNet; and an ensemble model of CNN with SVM. The ensemble CNN-SVM model is optimized using techniques such as feature aggregation and weight adjustments. Skin lesion images from Kaggle’s Human Against Machine 10000 (HAM10000) are used to train and test all classification models. Through rigorous experiments, the results highlight the compelling efficacy of the ensemble CNN-SVM model, unveiling heightened accuracy of up to 92% (from ResNet accuracy of 88%, CNN accuracy of 85%, SVM accuracy of 83%, LeNet-5 accuracy of 77%, and LDA accuracy of 75%). The models are tested on another dataset from Kaggle’s Melanoma Skin Cancer Dataset of 10000 Images; new results follow a similar trend to those using the HAM10000 dataset. The outcome of this work has profound implications for artificial intelligence (AI) accelerated engineering applications in advancing the effectiveness of skin disease treatment through diagnosis systems.

Protein-protein interaction (PPI) is an important field in bioinformatics which helps in understanding diseases and devising therapy. PPI aims at estimating the similarity of protein sequences and their common regions. STRIKE was introduced as a PPI algorithm which was able to achieve reasonable improvement over existing PPI prediction methods. Although it consumes a lower execution time than most of other state-of the-art PPI prediction methods, its compute-intensive nature and the large volume of protein sequences in protein databases necessitate further time acceleration. In this paper, we develop hardware accelerator designs for the STRIKE algorithm. Results indicate that the weighted STRIKE accelerator execution times are about 10x longer than the unweighted STRIKE accelerator execution times. To further accelerate the performance of the weighted STRIKE, a parallel module accelerator organization duplicating the weighted STRIKE modules is introduced, achieving near linear speedups for long sequences of 100 or more characters. As demonstrated by Verilog simulations and FPGA runs, the weighted STRIKE module accelerator exhibits three orders of magnitude speed improvement over multi-core and cluster computers. Much higher speedups are possible with the parallel module accelerator.

In this work, we introduce a software-defined unmanned aerial systems (UAS) model, which can provide access to sensitive places where Wi-Fi communication is most needed for rescue operations. The proposed UAS model is equipped with smart obstacle avoiding assistance and can navigate in a global positioning system (GPS) denied environments to accomplish rescue operations successfully. We conduct indoor simulations of the developed UAS model with mounted light detection and ranging (LIDAR) sensors. Although the experimental results suggest that a larger battery weight and a higher energy consumption are needed than theoretically estimated, the proposed UAS model shows promise to be used in smart disaster management.

Multicore architectures suffer from high core-to-core communication latency primarily due to the cache's dynamic behavior. Studies suggest that a directory-approach can be helpful to reduce communication latency by storing the cached block information. Recent studies also indicate that a wireless router has potential to help decrease communication latency in multicore architectures. In this work, we propose a directory based multicore architecture with wireless routers to minimize communication latency. We simulate systems with mesh (used in the Standford Directory Architecture for SHared memory (DASH) architecture), wireless network-on-chip (WNoC), and the proposed directory based architecture with wireless routers. According to the experimental results, our proposed architecture outperforms the WNoC and the mesh architectures. It is observed that the proposed architecture helps decrease the communication delay by up to 15.71 percent and the total power consumption by up to 67.58 percent when compared with the mesh architecture. Similarly, the proposed architecture helps decrease the communication delay by up to 10.00 percent and the total power consumption by upto 58.10 percent when compared with the WNoC architecture. This is due to the fact that the proposed directory based mechanism helps reduce the number of core-to-core communication and the wireless routers help reduce the total number of hops.

Both size and computational activities of Vehicular Area Network (VANET) are growing. Simulation of VANETs not only requires the simulation of network standards, but also requires the mobility of nodes. Such a dynamic system involves computations of node distances, routing protocols, application layers, data send, data receive, etc. The simulation model of VANET requires both hardware and software supports to deal with massive computational problems. Currently available network simulators, like Network Simulator 3 (NS-3), are not adequate for simulating large-scale VANET systems. In this work, we propose a Compute Unified Device Architecture (CUDA)-assisted VANET simulation model for multicore Central Processing Unit (CPU) / manycore Graphics Processing Unit (GPU) platform to increase computational throughput. The proposed VANET/GPU simulator uses NS-3 as the core engine and improves throughput by exploiting massively parallel processing on the GPU. Experimental results show that the overall computation speedup can be increased up to 129x by using the proposed VANET/GPU simulator.

Based on the recent design trend from giant chip-vendors, multicore systems are being deployed with multilevel caches to achieve higher levels of performance. Supporting real-time applications on multicore systems becomes a great challenge as caches are power hungry and caches make the execution time predictability worse. Studies show that timing predictability can be improved using cache locking techniques. However, level-1 (L1) entire locking may not be efficient if smaller amount of instructions/data compared to the cache size is locked. An alternative choice may be way locking. For some processors, way locking is possible at level-2 (L2) cache (not permitted at L1). Even though both L1 entire locking and L2 way locking improve predictability, it is difficult to justify the performance and power trade-off between these two locking mechanisms. In this work, we simulate a multicore system with two levels of caches to explore the impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability. Simulation results using FFT, DFT, and MPEG4 algorithms show that both performance and predictability can be increased and power consumption can be decreased by using a cache locking mechanism added to a cache memory hierarchy. Results also show that for FFT and DFT, L2 way locking outperforms L1 entire locking; but for MPEG4, L1 entire locking performs better than L2 way locking.

The computing power of microprocessors has exponentially increased in the past few decades and so is the support to computation intensive multimedia applications. With such improved computing power, memory subsystem deficiency becomes the major barrier to support video messaging and video telephony/conferencing on mobile handsets. Studies show that for multimedia applications there are sufficient reuses of values for caching and there is an opportunity for customizing the cache subsystem for improved performance. In our previous work, we optimized cache to enhance MPEG-4 (Part 2) decoding performance running on a mobile device. H.264/AVC (or MPEG-4 Part 10) outperforms both MPEG-4 (Part 2) and H.263 by providing better video quality at a lower bit-rate and a lower latency. As a result, H.264/AVC becomes the next generation video codec for embedded systems. In this paper, our focus is to enhance decoding performance of H.264/AVC through cache optimization for an embedded and mobile device. The simulated architecture includes a processor to run the decoding algorithm and a twolevel cache system. Level-1 cache is split into Instruction and Data caches and level-2 cache is a unified cache. We use Cachegrind to characterize H.264/AVC decoding workload and VisualSim to model the system-level architecture and run the simulation for H.264/AVC decoding workload. Simulation results show that H.264/AVC decoding performance can be enhanced through cache optimization.